Electronics Guide

Stages and Where They Sit

The chain begins with intellectual property and design: processor cores, interface blocks, and the full-chip designs that assemble them. This stage requires engineers and software rather than factories, and it clustered where engineering talent and capital already existed — the United States above all, with substantial concentrations in Britain, Israel, Taiwan, South Korea, China, and India.

Electronic design automation supplies the software that turns a hardware description into a manufacturable layout and verifies that it will work. Three firms dominate: Synopsys and Cadence, both headquartered in the San Francisco Bay Area, and Siemens EDA, the former Mentor Graphics of Wilsonville, Oregon, acquired by Siemens in 2017. Market trackers have put their combined share of design-tool revenue at around three-quarters for years; the exact number varies with how the category is drawn, but no reading of it leaves room for a fourth significant vendor.

Front-end fabrication converts blank silicon wafers into finished circuits through several hundred sequential process steps. This stage is the most capital-intensive part of the chain and the one that concentrated most severely. Assembly, test, and packaging, often abbreviated ATP or handled by outsourced firms known as OSATs, cuts the wafer into dice, connects them to a package, and verifies function. Historically labor-intensive, it migrated to lower-cost economies in Southeast Asia and China; advanced packaging has since pulled part of it back toward the fabs.

Supporting all of these are the equipment and materials industries: lithography scanners, deposition and etch chambers, metrology tools, silicon wafers, photomasks, photoresists, specialty gases, and package substrates. These sectors are smaller in revenue than chipmaking itself but contain the highest density of single-source dependencies in the entire chain.

Value and Volume Do Not Coincide

A common error is to equate the number of chips a region makes with its importance to the chain. Measured by installed wafer capacity, the industry looks reasonably distributed. An analysis published by the Semiconductor Industry Association and Boston Consulting Group in 2021 put 2019 capacity shares at roughly 22 percent for Taiwan, 21 percent for South Korea, 15 percent each for Japan and China, 12 percent for the United States, and 9 percent for Europe. China's share has risen substantially since, driven by aggressive investment in mature nodes.

Measured by capability, the picture changes completely. The same analysis found that Taiwan held 92 percent of the world's capacity for logic below ten nanometers. A region can hold a fifth of global wafer starts and still be unable to make a modern smartphone application processor or an artificial-intelligence accelerator. Conversely, a region can hold a small share of wafer starts and still be indispensable, as the Netherlands demonstrates with a lithography industry that produces no chips at all.

The United States illustrates the divergence from the other direction. Its share of global fabrication capacity fell from roughly 37 percent in 1990 to about 12 percent by the late 2010s, yet American firms continued to capture close to half of global semiconductor revenue through design, intellectual property, equipment, and software. Losing factories and losing the industry are different events, though the first can eventually cause the second if the design base drifts toward its manufacturing partners.

Why the Chain Fragmented

The geography described here is the product of deliberate corporate choices rather than accident. Until the 1980s, most semiconductor companies were integrated device manufacturers: they designed, fabricated, packaged, and sold their own chips. Fabrication costs then began to rise faster than the market, and a company that could not fill a leading-edge fab could not justify building one.

The foundry model resolved the tension. When Morris Chang founded Taiwan Semiconductor Manufacturing Company in 1987, he proposed a factory that would build other companies' designs and compete with none of its customers. Design houses could then abandon manufacturing entirely, and dozens did. The bargain worked: fabless firms shed the heaviest fixed costs, and the foundry aggregated demand from many customers to fill a fab that no single one of them could keep busy. The unavoidable consequence was that fabrication concentrated wherever the foundries were, because economies of scale in this business are enormous and largely unbounded within the range of realistic demand.

Fabless Design Clusters

Fabless design concentrated first in the United States, where the venture capital that funded the model and the universities that trained its engineers were already established. Nvidia, Qualcomm, Broadcom, Advanced Micro Devices, Marvell, and Apple's silicon group all design in the United States and manufacture almost entirely abroad. Israel hosts substantial design centers for both local firms and multinationals. Taiwan built its own fabless sector alongside its foundries, with MediaTek in Hsinchu among the largest mobile chip designers in the world. South Korea's design activity sits mainly inside Samsung and SK hynix. China's fabless sector grew rapidly from the 2000s, with HiSilicon, Unisoc, and a large tail of smaller firms.

India occupies a distinctive position. It has hosted design and verification centers for multinational semiconductor firms since the 1980s, when Texas Instruments opened in Bangalore, and a large fraction of the world's chip verification work is performed there. Until the 2020s, however, almost none of that design activity was accompanied by domestic fabrication, which made India a case study in how far a country can advance in the value chain without owning a single factory.

Processor Architectures and Licensed Intellectual Property

Few chip designers build every block themselves. Processor cores, memory controllers, physical interfaces, and analog blocks are commonly licensed. Arm Holdings, based in Cambridge, England, acquired by SoftBank in 2016 and returned to public listing on Nasdaq in September 2023 with SoftBank retaining a large majority of the shares, licenses the architecture that dominates mobile, embedded, and increasingly server processors. Its position makes a single British company a dependency for designers on every continent, and it is a dependency that governments have noticed: proposed acquisitions of Arm have drawn regulatory attention precisely because the architecture functions as shared infrastructure rather than an ordinary product.

RISC-V, an open instruction-set architecture that originated at the University of California, Berkeley, in 2010, represents a partial answer to that concentration. Because the specification is open and royalty-free, it cannot be embargoed in the way a proprietary license can. RISC-V International moved its incorporation to Switzerland in 2020, a decision that the organization presented as a matter of neutrality and that observers read as a response to export-control risk. The move illustrates a general point: some chokepoints can be dissolved by changing the licensing model rather than by building new factories.

Electronic Design Automation

Design software is a genuine chokepoint hiding in plain sight. Advanced chips cannot be designed, verified, or prepared for manufacture without the tool flows sold by Synopsys, Cadence, and Siemens EDA. The tools embed decades of accumulated modeling work, they are qualified jointly with each foundry's process, and no adequate substitute exists. Because the three leading vendors are American or American-rooted, design software has become a lever of export policy; restrictions on supplying certain classes of design tools to specified Chinese entities have accompanied the broader controls on manufacturing equipment.

Efforts to build alternatives exist, including open-source flows and domestic Chinese vendors such as Empyrean and Primarius, but the gap is widest exactly where it matters most: full sign-off flows for advanced nodes, where the tool must model physical effects that only the foundry fully characterizes. Design software therefore has a strange geography — it is written in a handful of buildings, distributed instantaneously worldwide, and yet controllable at the license server.

The Narrowing Field

At the 180-nanometer generation around the turn of the millennium, more than twenty companies operated leading-edge logic lines. At 45 nanometers the number had fallen to roughly a dozen. By the 7-nanometer generation only three companies could manufacture in volume, and that number has held: Taiwan Semiconductor Manufacturing Company, Samsung Electronics, and Intel.

Two departures from the race illustrate the economics. GlobalFoundries, spun out of Advanced Micro Devices in 2009 and expanded by the acquisition of Singapore's Chartered Semiconductor and IBM's manufacturing operations, announced in August 2018 that it would stop development of its 7-nanometer process and concentrate on differentiated mature technologies. United Microelectronics Corporation, Taiwan's second foundry, made a comparable decision the same year, ending investment below 14 nanometers. Neither company failed; both concluded that the return on a leading-edge node no longer justified the capital, and both have prospered since in specialty processes. Their exits nonetheless left the frontier to three firms.

The frontier itself has continued to advance. Gate-all-around transistors entered volume production at Samsung and then at TSMC, extreme ultraviolet lithography moved from introduction to routine use, and backside power delivery entered the roadmap at Intel and its competitors. Each of these transitions raised the cost of entry again, which is why the list of firms that can execute them has not lengthened.

Taiwan's Concentration

TSMC alone accounted for 69.9 percent of global foundry revenue across 2025 by TrendForce's accounting, up from 64.4 percent in 2024, and its share of leading-edge capacity is higher still. Its most advanced production sits within Taiwan's three science parks: Hsinchu in the north, the Central Taiwan Science Park at Taichung, and the Southern Taiwan Science Park at Tainan, with newer sites at Kaohsiung and Chiayi. These are not merely factory locations. They are clusters in the full sense, containing equipment vendors' service organizations, chemical suppliers, mask shops, packaging houses, and a labor market of process engineers who move among them.

Clustering of this density is the reason a fab cannot simply be copied elsewhere. A new fab in a new country arrives without the surrounding ecosystem: without the local gas supplier who can deliver on two hours' notice, without the spare-parts depot, without the contractor crews who have installed the same tool forty times. TSMC's experience building in Arizona, where the company publicly cited construction schedules, labor availability, and cost differentials as obstacles, made the point concrete. The company has proceeded regardless: the first Arizona fab entered volume production on a 4-nanometer process at the end of 2024, and TSMC has repeatedly enlarged its committed investment at the site since. It has proceeded in Kumamoto, Japan and Dresden, Germany as well. The projects have shown that geography carries more than land and electricity, and that the schedules published at groundbreaking are optimistic more often than not.

The concentration also creates the industry's most discussed strategic exposure. Taiwan's political situation and its position in a seismically active zone place a large fraction of the world's advanced computing capability in one contested and geologically restless place. Analysts have described the resulting deterrent effect as a “silicon shield,” a term that is contested precisely because it treats an industrial accident of history as a security policy.

Memory and the Korean Concentration

Memory follows a parallel pattern with a different map. Three firms — Samsung Electronics, SK hynix, and Micron Technology — supply the overwhelming majority of the world's dynamic random-access memory. Two of the three are Korean, and their principal fabs sit in a small area south of Seoul: Samsung at Hwaseong, Pyeongtaek, and Giheung; SK hynix at Icheon and Cheongju. NAND flash is somewhat less concentrated, adding Kioxia and its partner SanDisk with plants at Yokkaichi and Kitakami in Japan, and China's Yangtze Memory Technologies at Wuhan.

High-bandwidth memory, the stacked DRAM that feeds artificial-intelligence accelerators, tightened this concentration further in the 2020s. HBM requires through-silicon vias, precise die stacking, and package-level yields that only a few lines achieve, and the resulting supply became a limiting factor on accelerator production. SK hynix qualified first with the leading accelerator vendors and held the strongest position through the buildout; Samsung and Micron followed, and the three-supplier structure of commodity DRAM narrowed further at its most profitable end. The chain for a single AI accelerator therefore runs through Korea for memory, Taiwan for logic and advanced packaging, Japan for substrate materials, the Netherlands for lithography, and the United States for design — with no meaningful redundancy at any of those points.

The Mature-Node Layer

Attention naturally follows the leading edge, but most chips are not made there. Power devices, analog parts, microcontrollers, display drivers, image sensors, and the great majority of automotive semiconductors are built at nodes from 28 nanometers up to several micrometers, on equipment that in some cases has been depreciated for a decade. This layer is geographically broader: it includes Texas Instruments and Analog Devices in the United States, Infineon and STMicroelectronics in Europe, Renesas and Rohm in Japan, and a long list of Chinese, Taiwanese, and Korean suppliers.

It was this layer, not the leading edge, that failed during the automotive shortage of 2021. A modern vehicle contains hundreds to a few thousand semiconductors, and the overwhelming majority are mature parts costing a few dollars or less. When automakers cut orders in the spring of 2020 and foundries reallocated the freed capacity to consumer electronics, the automakers could not reclaim it, and vehicle production lines halted for want of components that no one had previously considered strategic.

China's investment has concentrated heavily in this layer, in part because export controls restrict its access to leading-edge equipment and in part because mature capacity serves domestic industrial demand. The resulting expansion has prompted concern in Europe and the United States about future dependence on Chinese mature-node supply for automotive and industrial parts — a dependence that would matter less for performance and a great deal for availability. Both jurisdictions have opened trade investigations into legacy-node chips, and the instruments under discussion are tariffs and procurement rules rather than the export controls used at the leading edge, because the concern is price and displacement rather than capability transfer.

ASML and Extreme Ultraviolet

ASML began in 1984 as a joint venture between Philips and ASM International, operating at first from a prefabricated building beside a Philips site in Veldhoven, in the southern Netherlands. For its first decade it was a marginal competitor to Nikon and Canon. Its rise to dominance came through a sequence of technical bets, of which the largest was extreme ultraviolet lithography.

EUV uses light at a wavelength of 13.5 nanometers, generated by striking droplets of molten tin with a high-power carbon dioxide laser tens of thousands of times per second to create a plasma. Because no material transmits usefully at that wavelength, the entire optical path uses multilayer molybdenum-silicon mirrors and operates in vacuum. Development consumed more than two decades and billions of euros, drawing on research consortia in the United States and Europe and on capital invested by Intel, Samsung, and TSMC in 2012. The result is that ASML is the only manufacturer of EUV scanners in the world, and every leading-edge logic and DRAM process now depends on tools from that one company. ASML also supplies the large majority of deep ultraviolet immersion scanners, so its position in lithography as a whole, not only at the frontier, is close to unchallenged.

The dependence runs deeper than the ASML nameplate. The optics come from Carl Zeiss SMT in Oberkochen, Germany, in which ASML took a 24.9 percent stake in 2016; the mirrors are among the most precisely figured surfaces ever manufactured. The carbon dioxide drive laser comes from Trumpf in Ditzingen, also in Germany. The light source integrating them descends from Cymer of San Diego, which ASML acquired in 2013. A single EUV scanner contains on the order of a hundred thousand parts drawn from a supplier network of several hundred firms, which means the chokepoint is not one company but a tightly coupled international consortium with almost no substitutability at any layer.

High Numerical Aperture and the Next Step

The successor generation raises the numerical aperture of the projection optics from 0.33 to 0.55, improving resolution at the cost of a smaller printed field that must be stitched from two exposures. ASML shipped the first High-NA research system, the EXE:5000, to Intel in December 2023, and a second to TSMC in late 2024; the EXE:5200 is the configuration intended for high-volume manufacturing. ASML does not publish list prices, but the tools have been reported at roughly $370 million each, on the order of double a standard EUV scanner, and a single machine ships as a set of modules that fills several freight aircraft.

Prices at that level have a geographic consequence. Only firms with the largest capital budgets can adopt the tool at all, which reinforces the existing concentration rather than relieving it. Intel positioned early High-NA adoption as a route back to process leadership; TSMC has signaled a more cautious schedule, arguing that multi-patterning with existing EUV remains more economical for longer. Either way, the number of companies that can buy the frontier tool is smaller than the number that could buy its predecessor.

Deposition, Etch, Metrology, and Implantation

Lithography receives the attention, but a fab contains hundreds of other tools, and their supply is also concentrated — in the United States and Japan rather than in Europe. Applied Materials of Santa Clara and Lam Research of Fremont lead in deposition and etch respectively; KLA of Milpitas leads in process control and inspection; Tokyo Electron holds strong positions in coater-developers, etch, and deposition; ASM International of Almere leads in atomic layer deposition. Together with ASML, these five firms account for a substantial majority of wafer fabrication equipment revenue.

The distribution of this equipment base explains why export controls have been coordinated among a small group of governments. Restrictions imposed by the United States alone would leave Japanese and Dutch alternatives available; restrictions coordinated among the United States, Japan, and the Netherlands cover nearly the entire capable supply. The Japanese Ministry of Economy, Trade and Industry added twenty-three categories of semiconductor manufacturing equipment to its license requirements in a rule announced in March 2023 and effective in July of that year, and the Netherlands introduced licensing for certain advanced immersion lithography systems effective September 2023, widening the covered categories again with effect from January 2025. Neither measure named a destination country, and both were understood in the same terms.

Silicon Wafers

Every chip begins as a polished monocrystalline silicon wafer, grown by the Czochralski method from electronic-grade polysilicon and finished to a flatness measured in nanometers. Five companies supply nearly the whole market: Shin-Etsu Chemical and SUMCO in Japan, which together hold roughly half of global wafer supply; GlobalWafers of Taiwan; Siltronic of Germany; and SK Siltron of South Korea. Concentration is even higher for 300-millimeter wafers destined for leading-edge lines, where qualification requirements exclude marginal suppliers.

The wafer chain reaches further back than most maps show. Growing a silicon boule requires a fused-quartz crucible, and the highest-purity quartz sand suitable for the innermost crucible layer comes overwhelmingly from deposits around Spruce Pine, North Carolina. When Hurricane Helene struck western North Carolina in September 2024 and suspended operations there, the disruption drew attention to a dependency that even specialists had rarely articulated. Operations resumed within weeks and no wafer shortage followed, which is itself instructive: the exposure was real, the buffer stocks held, and the episode functioned as a warning rather than a failure.

Photoresists and Photomask Materials

Photoresist — the light-sensitive polymer that records the projected pattern — is a Japanese specialty. JSR, Tokyo Ohka Kogyo, Shin-Etsu, Fujifilm, and Sumitomo Chemical hold the great majority of the global market, and their combined share of resists qualified for EUV exposure approaches totality. The reasons are historical and cumulative: resist formulation is a chemistry discipline in which decades of proprietary knowledge produce advantages that a well-funded newcomer cannot replicate quickly, and each new lithography generation is co-developed with the same suppliers.

Photomask materials follow the same pattern. EUV mask blanks — the coated quartz substrates onto which the pattern is written — come almost entirely from Hoya and AGC of Japan, with each blank requiring a defect-free multilayer coating of extraordinary quality. EUV pellicles, the thin protective membranes that keep particles off the mask, and a range of ultrahigh-purity process chemicals show comparable concentration.

Japan demonstrated what this position permits in July 2019, when it imposed licensing requirements on exports to South Korea of three materials: fluorinated polyimide, photoresists, and hydrogen fluoride. The dispute originated in wartime-labor litigation rather than in technology policy, but its instrument was the materials chain. South Korean firms responded with a domestic substitution program that reduced, though did not eliminate, the dependency, and the controls were relaxed in 2023. The episode remains the clearest demonstration that materials supply can be used as leverage, and that recovering from such leverage takes years rather than weeks.

Industrial Gases and the Neon Lesson

Fabs consume large volumes of specialty gases: nitrogen, argon, helium, hydrogen, and a long list of etchants and precursors. Most are produced regionally because transporting them is expensive. Neon is the exception that taught the industry a lesson.

Neon fills the excimer lasers used in deep ultraviolet lithography. It is separated from air, but economically only as a byproduct of large-scale air separation of the kind operated alongside steel plants, and the Soviet Union built such capacity in what is now Ukraine. Before 2022, two Ukrainian producers — Ingas in Mariupol and Cryoin in Odesa — were reported to supply roughly half of the world's semiconductor-grade neon, a share drawn from market-research estimates rather than any published statistic. Both halted production in March 2022 following the Russian invasion. Prices rose by an order of magnitude, and although catastrophic shortages did not materialize, the industry spent the following two years qualifying alternative supply, including new extraction capacity at Korean steelworks. The episode showed that a chokepoint can arise not from technological difficulty but from where a byproduct happens to be captured.

Critical Minerals and Export Controls

Compound semiconductors and specialty processes depend on elements whose refining has concentrated in China. Gallium is essential to gallium nitride and gallium arsenide devices; germanium goes into infrared optics, fiber-optic components, and silicon-germanium processes. The United States Geological Survey estimated that China accounted for 98 percent of world primary low-purity gallium production in 2024, and China is likewise the dominant refiner of germanium. Neither element is geologically scarce. Both are recovered as byproducts — gallium from bauxite processing, germanium chiefly from zinc residues and coal fly ash — and the concentration reflects where the host industries and the refining capacity happen to sit rather than where the elements occur.

China announced licensing requirements for gallium and germanium exports on July 3, 2023, effective August 1 of that year, and extended comparable controls to antimony and superhard materials effective September 15, 2024. On December 3, 2024, it barred exports of gallium, germanium, and antimony to the United States outright. Further controls on several medium and heavy rare-earth elements followed in April 2025. Each measure was presented as a national-security provision and read internationally as a response to semiconductor export restrictions. Whatever the intent, the sequence established that the upstream mineral chain is a two-way instrument, and that the leverage runs in the opposite direction from the equipment controls.

The Assembly Belt

American semiconductor firms began offshoring assembly in the early 1960s, when Fairchild opened a plant in Hong Kong and later in Penang, Malaysia. Penang grew into one of the world's dominant assembly and test centers and retains that position, alongside the Philippines, Thailand, Vietnam, Singapore, and above all Taiwan and China.

The outsourced assembly and test sector is led by ASE Technology Holding of Taiwan, the largest such firm by a wide margin, followed by Amkor Technology, an American company whose operations are concentrated in Korea, the Philippines, Vietnam, and elsewhere in Asia, and by JCET of China. Taiwan and China together handle the majority of outsourced assembly and test volume. The stage remains more distributed than fabrication, and firms can shift work between sites with far less difficulty, but the aggregate weight still sits in East and Southeast Asia.

Advanced Packaging as a New Chokepoint

As transistor scaling slowed, performance gains shifted toward integrating multiple dice in one package. Two-and-a-half-dimensional interposers, three-dimensional stacking, and chiplet architectures now determine the capability of high-end processors as much as the transistor node does.

TSMC's chip-on-wafer-on-substrate process, which places logic dice and high-bandwidth memory stacks on a silicon interposer, became the binding constraint on artificial-intelligence accelerator supply during the mid-2020s. Demand exceeded capacity for an extended period, and the constraint was not wafer starts at the leading edge but packaging throughput at a small number of Taiwanese facilities. The industry had spent thirty years treating packaging as the easy part of the chain and then discovered that its most advanced form had become as concentrated as fabrication, and located in the same place.

Package substrates show the same pattern one level down. The build-up film used in the substrates that carry high-performance processors is an Ajinomoto product — the company better known for food seasoning developed it from resin chemistry — and it has no equivalent competitor. The substrates themselves come chiefly from Ibiden and Shinko Electric in Japan, Unimicron and Nanya in Taiwan, Samsung Electro-Mechanics and LG Innotek in Korea, and AT&S in Austria. Substrate shortages contributed materially to the component shortages of 2021 and 2022, and they received far less attention than the fabs.

The Conditions

The first condition is high fixed cost relative to market size. When the investment required to serve a market approaches the market's total value, only one or two suppliers can be sustained. EUV lithography is the extreme case: a development program costing billions serves an addressable market of a few hundred machines a year.

The second is tacit process knowledge. Much of what makes an advanced process work is not written down. It resides in the judgment of engineers who have watched a particular tool drift over five years. Such knowledge transfers only by moving people, which is why new fabs in new regions are commonly staffed initially by expatriates from the parent site.

The third is long qualification cycles. A new photoresist, a new wafer supplier, or a new substrate vendor must be qualified into a process flow, and qualification for a demanding application can take one to three years. Automotive and aerospace qualification takes longer still. A chokepoint that could in principle be substituted in eighteen months is, during a crisis lasting six, indistinguishable from one that cannot be substituted at all.

The fourth is network coupling. A supplier that is itself dependent on a single upstream source transmits rather than absorbs risk. ASML's dependence on Zeiss optics and Trumpf lasers is the canonical example: three companies in two countries constitute one effective chokepoint.

A fifth condition is invisibility. A dependency that no purchasing system records cannot be managed, and the deepest ones are usually recorded nowhere, because they sit several tiers upstream inside a component that appears on the bill of materials as a single line item. The quartz crucible, the mask pellicle, and the substrate build-up film all belong to this category. They became visible only when something interrupted them, which is the defining property of the class and the reason mapping exercises keep finding new members.

Geographic Concentration Versus Corporate Concentration

The two are frequently conflated and behave differently. A single company operating on three continents presents corporate concentration without geographic concentration: an antitrust or export-control problem, but not necessarily an earthquake problem. Several companies operating in one industrial park present the reverse: competitive markets that fail simultaneously in a regional disaster.

The distinction matters for mitigation. Corporate concentration is addressed by encouraging entrants, licensing technology, or regulating conduct. Geographic concentration is addressed by building capacity elsewhere, which is slower and more expensive but yields resilience that a second supplier in the same industrial park does not. The most acute risks in the semiconductor chain, unfortunately, combine both: one company, in one place, making a product with no substitute.

The Shortage of 2020 to 2023

The pandemic-era shortage began with a demand shock rather than a supply failure. Automakers cut orders as sales collapsed in early 2020; consumer electronics demand surged as populations worked and studied from home; foundries reallocated capacity accordingly. When vehicle sales recovered faster than expected, the capacity was gone, and lead times for mature automotive parts stretched from weeks to a year or more. Manufacturers built vehicles without features, parked unfinished inventory awaiting chips, and in some cases halted assembly lines outright. Consultancy estimates of the lost revenue to the global automotive industry in 2021 alone ran to roughly $210 billion; the figure is a projection built on assumed production shortfalls rather than an audited total, but no serious estimate placed the loss below the tens of billions.

The episode revealed how little visibility firms had into their own supply chains. Automakers bought from tier-one system suppliers who bought from component makers who bought from distributors who bought from foundries. Few automakers could name the fab that made a part on which their production depended, and the mapping exercises that followed frequently discovered that supposedly independent suppliers converged on the same source three tiers upstream.

Single-Site Failures

Three events in 2021 demonstrated the fragility of individual sites. In February, winter storm Uri knocked out power across Texas and forced shutdowns at Samsung's Austin fab and at NXP and Infineon facilities, destroying work in progress and costing months of output. In March, a fire in a 300-millimeter line at Renesas Electronics' Naka plant in Ibaraki Prefecture damaged equipment producing automotive microcontrollers; recovery to full output took roughly three months and worsened the automotive shortage. Through the same year, Taiwan experienced its worst drought in more than half a century, and fabs that consume on the order of ten million liters of ultrapure water a day were supplied in part by tanker truck.

Seismic exposure is a permanent feature rather than an event. An earthquake off Hualien on April 3, 2024, measured at magnitude 7.4 by the United States Geological Survey, prompted evacuations and tool shutdowns across Taiwanese fabs. Damage proved limited — Taiwanese facilities are engineered for exactly this — but the incident cost TSMC a reported few billion New Taiwan dollars in the following quarter and served as a reminder of what a larger or closer event might do. Japan's fabs face the same exposure, as the industry was reminded when earthquakes in Kumamoto Prefecture interrupted operations there.

Export Controls as a Deliberate Shock

Beginning in 2018, the United States moved from case-by-case enforcement to systematic restriction of semiconductor technology flows to China. The Entity List additions affecting Huawei in 2019, and the foreign direct product rule extended in 2020, cut a major designer off from foundry service. On October 7, 2022, the Bureau of Industry and Security issued a rule that restricted advanced computing chips and semiconductor manufacturing equipment far more broadly, and added restrictions on United States persons supporting Chinese advanced fabrication. Revisions followed in October 2023 and December 2024, the latter extending controls to high-bandwidth memory and additional equipment categories.

The controls transformed supply chain geography from a description into a policy variable. Firms redesigned products to fall below performance thresholds; Chinese firms accelerated domestic substitution; equipment vendors lost a large market and gained a compliance department. Whether the controls will durably slow Chinese capability or mainly accelerate an independent Chinese chain is genuinely contested, and the honest answer in the mid-2020s is that the evidence supports both readings in different segments.

The United States

The CHIPS and Science Act, signed on August 9, 2022, appropriated $52.7 billion for semiconductor manufacturing incentives, research, and workforce development, of which roughly $39 billion supported manufacturing and about $11 billion supported research programs including the National Semiconductor Technology Center. Separately, the law created an investment tax credit for semiconductor fabrication facilities, initially set at 25 percent and raised to 35 percent by the reconciliation law signed on July 4, 2025. Unlike the grant program, the credit is claimed rather than awarded, so its total cost depends on how much qualifying investment is actually made.

Preliminary memoranda of terms were announced through 2024 and converted into binding agreements late that year, among them TSMC, Samsung, Micron, GlobalFoundries, and Intel, with projects concentrated in Arizona, Texas, Ohio, New York, and Idaho. The distinction between announced and finalized amounts is not pedantic: several headline figures were reduced between announcement and signature, and Intel's award fell from an announced $8.5 billion to $7.86 billion.

The program was then reworked. In August 2025 the federal government converted Intel's remaining grant commitments into equity, purchasing 433.3 million shares at $20.47 for approximately $8.9 billion and taking a stake of 9.9 percent in the company, with a warrant for a further tranche attached. Whether that arrangement is best read as industrial policy, as a rescue of a single firm, or as a precedent for state shareholding in strategic manufacturers is genuinely disputed, and the disagreement does not divide neatly along partisan lines.

Europe

The European Chips Act entered into force in September 2023, seeking to mobilize approximately €43 billion in public and private investment and setting a target of raising Europe's share of world semiconductor production to 20 percent by 2030. The target has not survived contact with arithmetic. Reaching it would require European output to grow several times over while global output also grows, and the European Commission's own 2024 projection put the likely 2030 share near 12 percent. The European Court of Auditors reported in 2025 that the measures in place were very unlikely to be sufficient to meet the target, and criticized the absence of clear operational milestones against which progress could be judged.

The project list has also thinned. Intel's proposed site at Magdeburg, the largest single investment associated with the act, was postponed in September 2024 and cancelled outright in July 2025 as part of a company-wide retrenchment, taking a planned packaging plant in Poland with it. What remains is substantial but more modest and more conventional: the ESMC joint venture at Dresden, in which TSMC holds the majority alongside Bosch, Infineon, and NXP, broke ground in August 2024 to build mature and mid-range nodes for European automotive and industrial customers, and STMicroelectronics and Infineon have expanded capacity in France, Italy, and Germany. The pattern is consistent with the historical record: the projects that proceeded were extensions of businesses that already existed in Europe, and the one that collapsed was the greenfield leap.

Japan, Korea, and India

Japan pursued the most striking reversal. Having lost leading-edge logic decades earlier, the country subsidized TSMC's Kumamoto joint venture with Sony and Denso, which opened in February 2024 and reached commercial production of 12- to 28-nanometer processes in December of that year, with a second, more advanced fab on the same site following behind its original schedule, and simultaneously founded Rapidus in August 2022 to attempt 2-nanometer manufacturing in Hokkaido with technology from IBM and imec. Rapidus began operating a pilot line at Chitose in April 2025 and showed 2-nanometer gate-all-around test wafers from it in July of that year, with mass production targeted for 2027 — an unusually direct attempt to re-enter a frontier that no company has re-entered before.

South Korea announced its K-Semiconductor strategy in 2021, combining tax incentives with infrastructure for a large cluster around Yongin. India approved its Semiconductor Mission in December 2021 with an outlay of about $10 billion, subsequently approving Micron's assembly and test plant at Sanand and a fab at Dholera in partnership between Tata Electronics and Taiwan's Powerchip, aimed at mature nodes rather than the leading edge — a realistic sequencing choice given the absence of an existing ecosystem.

China's program predates the others. The National Integrated Circuit Industry Investment Fund launched in 2014 and was followed by a second phase in 2019 and a third, capitalized at roughly 344 billion yuan, in May 2024. Combined with local government funds and directed lending, the effort has produced a large mature-node industry, a leading domestic foundry in SMIC, growing memory production, and a domestic equipment sector that remains well behind the frontier but is no longer negligible.

What Subsidies Can and Cannot Move

The analysis that framed much of this policy debate came from the Semiconductor Industry Association and Boston Consulting Group in 2021, which estimated that building fully self-sufficient regional supply chains would require at least $1 trillion in incremental upfront investment and would raise semiconductor prices by 35 to 65 percent. The estimate is a projection rather than a fact, and its assumptions are debatable, but its direction is not seriously disputed: complete regional self-sufficiency is achievable only at a cost that no government has proposed to pay.

What subsidies can plausibly achieve is narrower and still valuable: a second source for critical categories, domestic capacity sufficient for defense and essential infrastructure, and retention of the engineering base that makes future capability possible. The historical record suggests that public programs succeed when they reinforce an advantage a region already holds — an existing supplier base, a pool of process engineers, a nearby customer — and disappoint when they attempt to conjure an ecosystem from a greenfield site. The same pattern held for Japan's VLSI project, for SEMATECH, and for Taiwan's Industrial Technology Research Institute, each of which built on foundations that already existed.

Map Beyond the First Tier

Most firms know their direct suppliers and few know their suppliers' suppliers. The disruptions of 2021 repeatedly revealed convergence at the third or fourth tier, where two nominally independent sources turned out to share a fab, a substrate vendor, or a single specialty chemical. Mapping to the fab and wafer level for critical components, and recording the site rather than only the corporate name, is the prerequisite for every other mitigation.

Qualify Alternatives Before the Crisis

Second sources are useful only if they are qualified. Because qualification takes months to years, the decision to qualify an alternative must be made while supply is comfortable. Design practices that ease substitution — using parts with genuine drop-in equivalents, avoiding architectures that depend on one vendor's unique peripheral set, and keeping footprint compatibility in mind — cost little at design time and are nearly impossible to retrofit under pressure.

Match Inventory Policy to Chokepoint Depth

Just-in-time inventory is efficient against ordinary variability and defenseless against a single-source failure with a long recovery time. Rational policy distinguishes between components with several qualified sources, for which lean inventory is appropriate, and components that trace to a single site, for which strategic buffers, lifetime buys, or last-time-buy planning may be warranted. The relevant variable is not the part's cost but the time required to recover from losing it.

Treat Geography as a Design Input

Selecting a process node is also a decision about where a product will be manufactured and under which export-control regime it will fall. A design that requires a leading-edge node commits its owner to one of three companies and, for the most advanced nodes, largely to one island. A design that can meet its requirements at 28 or 40 nanometers has access to a broad and geographically diverse supplier base. Engineers rarely frame node selection this way, but the choice carries the geographic exposure that later becomes a procurement problem.