Electronics Guide

USB Physical Layer EMC Characteristics

USB employs differential signaling to improve noise immunity and reduce electromagnetic emissions. The differential pair carries data while a third conductor provides ground reference. However, common-mode currents on USB cables are a primary source of radiated emissions:

Low-speed and full-speed USB (1.5/12 Mbps): These modes use relatively slow edge rates with spectral content primarily below 100 MHz. EMC concerns focus on harmonics of the 12 MHz signaling frequency and common-mode noise from the host controller.

High-speed USB 2.0 (480 Mbps): The 480 MHz signaling rate produces significant spectral content into the GHz range. Source impedance matching becomes critical, and cable quality significantly affects both signal integrity and EMC performance.

SuperSpeed USB 3.x (5-20 Gbps): USB 3.0 and later versions use a separate set of differential pairs operating at multi-gigabit rates. The higher frequencies require careful attention to transmission line design, and the simultaneous operation of USB 2.0 and SuperSpeed modes on the same connector creates additional complexity.

USB4 (40 Gbps): Operating over Thunderbolt-compatible physical layer, USB4 pushes EMC requirements to their limits with extremely fast edge rates and tight channel loss budgets.

USB Connector and Cable EMC

USB cables act as unintentional antennas for common-mode currents generated by the host and device circuitry. Several mechanisms contribute to these currents:

• Ground noise: Voltage differences between host and device ground references drive common-mode current on the cable shield
• Differential-to-common-mode conversion: Imbalance in the differential drivers or routing converts differential signals to common-mode noise
• Cable resonance: Cables of certain lengths resonate at specific frequencies, greatly amplifying radiation at those frequencies

Mitigation strategies include common-mode chokes on USB lines near the connector, proper grounding of cable shields through 360-degree termination, and maintaining tight differential pair balance in PCB routing. For USB 3.x and USB4, high-frequency ferrites and careful connector selection become essential.

USB EMC Testing Requirements

USB certification requires passing both conducted and radiated emissions tests, as well as immunity testing. The USB Implementers Forum (USB-IF) specifies additional EMC requirements beyond standard regulatory compliance:

• Radiated emissions testing per CISPR 32 or FCC Part 15
• Conducted emissions on the power bus
• ESD immunity at the connector per IEC 61000-4-2
• Specific jitter and eye diagram requirements that implicitly control emissions

USB 3.x introduced additional concerns about interference with the 2.4 GHz WiFi and Bluetooth bands. The fundamental frequency and harmonics of USB 3.0 signaling fall within or near these bands, requiring careful attention to shielding and filtering.

HDMI EMC Considerations

High-Definition Multimedia Interface (HDMI) uses transition-minimized differential signaling (TMDS) to reduce EMI while maintaining signal integrity over consumer-grade cabling. Key EMC aspects include:

TMDS encoding: The encoding scheme reduces transitions and DC balance, which helps control spectral content. However, the high data rates (up to 48 Gbps for HDMI 2.1) still produce substantial high-frequency energy.

Cable shielding requirements: HDMI cables require comprehensive shielding to meet emissions requirements. Premium High Speed and Ultra High Speed cables use improved shielding and tighter construction tolerances.

Hot-plug detection: The hot-plug detect signal can cause transient emissions during cable connection. ESD protection on this line is essential, and the circuit should be designed to minimize switching noise.

DDC channel: The Display Data Channel uses I2C-like signaling for EDID communication. While low-speed, improper implementation can contribute to emissions and susceptibility issues.

Common HDMI EMC problems include radiation from inadequately shielded cables, ground loops between source and display causing hum bars in the video, and interference with wireless systems from the high-frequency TMDS signals.

DisplayPort EMC Characteristics

DisplayPort uses a packet-based protocol with more aggressive encoding and higher lane rates than HDMI. EMC considerations include:

Main link signaling: DisplayPort uses HBR (High Bit Rate) modes up to HBR3 at 8.1 Gbps per lane, with four lanes providing 32.4 Gbps total. The 8b/10b or 128b/132b encoding provides DC balance and limits run length.

AUX channel: The auxiliary channel handles link training and DPCD (DisplayPort Configuration Data) communication at lower speeds but requires proper termination and filtering.

Hot-plug detection: Similar to HDMI, the HPD signal requires ESD protection and careful design to prevent transient emissions.

DP Alt Mode over USB-C: When DisplayPort signals travel over USB Type-C connectors, the EMC requirements of both standards must be satisfied simultaneously, often requiring additional filtering and careful attention to ground plane design.

Video Interface EMC Mitigation

Common mitigation techniques for video interfaces include:

• Common-mode filtering: Integrated common-mode filters or discrete chokes reduce cable radiation
• Connector shielding: Metal connector shells must make solid contact with cable shields and chassis ground
• Ground plane continuity: Maintaining continuous ground planes under high-speed traces minimizes common-mode generation
• Pre-emphasis and equalization: Proper signal conditioning improves eye diagrams, indirectly improving EMC by allowing lower transmit amplitudes
• Spread spectrum clocking: Spreading clock energy across a wider bandwidth reduces peak emissions

PCIe Signal Characteristics

PCIe uses differential signaling with increasing lane rates through successive generations:

• PCIe Gen 1: 2.5 GT/s per lane with 8b/10b encoding (2.0 Gbps effective)
• PCIe Gen 2: 5.0 GT/s per lane (4.0 Gbps effective)
• PCIe Gen 3: 8.0 GT/s per lane with 128b/130b encoding (7.88 Gbps effective)
• PCIe Gen 4: 16.0 GT/s per lane (15.75 Gbps effective)
• PCIe Gen 5: 32.0 GT/s per lane (31.5 Gbps effective)
• PCIe Gen 6: 64.0 GT/s per lane with PAM4 signaling (63 Gbps effective)

The reference clock architecture significantly affects EMC. PCIe can use common clock, data clock, or separate reference clock architectures, each with different implications for spread spectrum clocking and jitter tolerance.

PCIe Connector and Slot EMC

PCIe edge connectors present unique EMC challenges:

Slot resonance: The PCIe slot and card edge form a transmission line structure that can resonate at frequencies determined by the slot length and card insertion depth. These resonances can amplify specific frequency emissions.

Ground plane coupling: The card ground planes must couple effectively to the motherboard ground through the connector pins. Insufficient grounding increases common-mode emissions.

Add-in card emissions: Graphics cards and other high-power add-in cards often dominate system emissions due to their high-speed circuits and large current demands. The card-to-motherboard interface is a common coupling path.

Cable-connected PCIe (as in external graphics enclosures) requires careful attention to cable shielding and connector design to maintain EMC compliance while preserving signal integrity.

PCIe EMC Design Practices

Effective PCIe EMC design involves:

• Reference plane continuity: High-speed differential pairs must reference continuous ground or power planes without slots or splits
• Via stub minimization: Back-drilling or controlled-depth drilling reduces via stubs that can resonate at high frequencies
• Spread spectrum clocking: Most PCIe implementations use spread spectrum on the reference clock to reduce peak emissions at clock harmonics
• AC coupling capacitor placement: The required AC coupling capacitors must be placed close to the transmitter to block DC while maintaining signal integrity
• Lane reversal and polarity: PCIe supports lane reversal and polarity inversion, which can simplify routing and improve EMC by allowing optimal trace paths

SATA EMC Characteristics

SATA uses point-to-point differential signaling with relatively relaxed timing requirements compared to other high-speed interfaces:

Spread spectrum clocking: SATA specification allows for spread spectrum clock modulation to reduce peak emissions. Most implementations use down-spreading of 0.5% to stay within the specification while reducing EMI.

Cable shielding: SATA cables use individual shielding for each differential pair plus an overall shield. The quality of this shielding significantly affects emissions, particularly for longer cables.

Connector grounding: Both internal and external SATA (eSATA) connectors require proper ground contact for shielding effectiveness. The latch mechanism affects shield continuity during cable flexing.

SAS EMC Requirements

SAS operates in enterprise environments with stricter EMC requirements and higher data rates:

Expander topologies: SAS allows complex topologies with expanders, creating multiple potential paths for EMI coupling between devices.

Backplane design: SAS backplanes in storage arrays must maintain signal integrity while managing emissions from multiple high-speed lanes operating simultaneously.

External SAS cables: Mini-SAS and Mini-SAS HD cables require comprehensive shielding and proper termination to meet emissions requirements in data center environments.

Copper Ethernet EMC

Copper Ethernet implementations face significant EMC challenges due to the combination of high data rates and unshielded or minimally shielded cabling:

10/100/1000BASE-T: These standards use transformer isolation at the physical layer, providing excellent common-mode rejection and galvanic isolation. The Bob Smith termination (center-tap termination through resistors to chassis ground) provides additional common-mode noise reduction.

Magnetics selection: The isolation transformer (magnetic module) critically affects EMC performance. Key parameters include common-mode rejection ratio, isolation voltage, and insertion loss. Auto-MDIX capability requires symmetric magnetics design.

2.5/5/10GBASE-T: Higher-speed copper Ethernet pushes category cabling to its limits. The increased transmit power and wider bandwidth create greater emissions potential, requiring careful attention to cable quality and length.

Power over Ethernet (PoE): PoE introduces DC power on the Ethernet cable, creating additional EMC considerations for power supply noise and potential ground loops. IEEE 802.3bt (90W PoE) requires particularly careful design to manage switching noise.

Industrial Ethernet EMC

Industrial Ethernet variants face harsher electromagnetic environments:

EtherNet/IP and PROFINET: These protocols run standard Ethernet physical layers but operate in factory environments with motors, drives, and other noise sources. Enhanced immunity requirements typically require shielded cabling and careful grounding.

Single-pair Ethernet: Emerging standards like 10BASE-T1S and 100BASE-T1 use single twisted pairs for automotive and industrial applications. These specifications include stringent EMC requirements appropriate for their intended environments.

Fiber Ethernet EMC

Fiber optic Ethernet provides inherent immunity to electromagnetic interference in the transmission medium, but the transceivers require attention:

Transceiver emissions: SFP, SFP+, QSFP, and other optical transceivers contain high-speed electronics that can emit EMI. The transceiver cage design and grounding affect overall system EMC.

Laser safety: While not strictly an EMC issue, optical transceivers must meet laser safety requirements that can affect enclosure design and potentially EMC.

Thunderbolt Physical Layer EMC

Thunderbolt 3 and 4 operate at up to 40 Gbps bidirectional over copper cables, with Thunderbolt 5 reaching 120 Gbps:

High-frequency emissions: The extremely fast edge rates produce significant spectral content well into the microwave frequency range. Maintaining emissions compliance requires excellent shielding throughout the signal path.

Active cables: Longer Thunderbolt cables often include active electronics (retimers) that can themselves contribute to emissions. Active cable EMC must be considered as part of the system design.

Protocol tunneling: Thunderbolt tunnels multiple protocols (PCIe, DisplayPort, USB) simultaneously. The aggregate emissions from all tunneled protocols must be managed.

Power Delivery EMC

Thunderbolt cables can deliver up to 240W of power (Extended Power Range), creating substantial power conversion EMC challenges:

• USB-PD communication: The Power Delivery protocol communicates over the CC (Configuration Channel) pins. This low-frequency signaling can couple with high-speed data if not properly filtered.
• Switching converter noise: High-power USB-PD chargers and hosts contain switching converters that can inject noise onto the cable and potentially couple to high-speed data lines.
• Cable-based power conversion: Some active cables include power conversion electronics that must meet EMC requirements within the cable assembly.

SerDes Architecture and EMC

Modern SerDes circuits include several features that affect EMC:

Pre-emphasis and de-emphasis: These transmitter features boost high-frequency content to compensate for channel losses. While improving signal integrity, they can increase emissions at those frequencies if not properly matched to the channel.

Equalization: Receiver equalization (CTLE and DFE) allows operation with lower transmit amplitudes, potentially reducing emissions. However, the additional high-speed circuitry in equalizers can itself contribute to noise.

Clock and data recovery (CDR): The CDR circuit extracts timing from the data stream. CDR loop bandwidth affects jitter tolerance and, indirectly, the immunity of the receiver to external interference.

Power supply sensitivity: SerDes circuits are sensitive to power supply noise, which can cause jitter that affects both signal integrity and emissions. Careful power supply filtering and decoupling are essential.

SerDes Clocking EMC

The clocking architecture significantly impacts SerDes EMC:

Reference clock distribution: The reference clock feeding the SerDes PLL must be low-jitter and well-isolated from noise. Clock distribution traces require controlled impedance and shielding from adjacent signals.

PLL phase noise: Phase noise from the SerDes PLL translates to jitter and can affect both emissions (through spectral spreading) and immunity (through timing margin reduction).

Spread spectrum clocking: Many SerDes implementations support spread spectrum clock modulation. The modulation profile affects both the emissions reduction achieved and the additional jitter introduced.

Optical Transceiver EMC

Optical transceivers convert between electrical and optical signals, with EMC considerations at the electrical interface:

High-speed electrical interface: The SerDes interface to the optical transceiver operates at the same high speeds as the optical link (10, 25, 100 Gbps or higher). This electrical interface requires the same EMC attention as any high-speed serial link.

Transceiver cage design: SFP, QSFP, and other transceiver cages must provide effective shielding while allowing thermal management. The cage-to-PCB interface affects both signal integrity and EMC.

Management interface: The I2C-based management interface (for Digital Diagnostic Monitoring) requires filtering to prevent coupling with high-speed signals.

Active Optical Cables

Active optical cables (AOCs) include transceivers at each end of a fiber cable, providing a solution that combines optical immunity with easy installation:

EMC advantages: AOCs eliminate the antenna effect of copper cables, significantly reducing radiated emissions and improving immunity.

Power considerations: AOCs require power at each end, typically delivered through the host connector. The power delivery path can still carry conducted emissions.

Certification: AOCs must be certified as complete assemblies, as the electronics at each end affect overall EMC performance.

Compliance Testing Programs

Most high-speed serial interfaces have industry compliance testing programs:

• USB-IF certification: Mandatory for using USB logos, includes electrical testing and increasingly rigorous EMC requirements
• HDMI certification: Required for HDMI branding, includes specific EMC and signal quality tests
• DisplayPort certification: VESA certification program with electrical and EMC testing
• Ethernet Alliance certification: Interoperability and compliance testing for Ethernet products
• PCI-SIG compliance: Required for PCIe devices, focuses on signal integrity but affects EMC

Test Equipment and Methods

Testing high-speed serial links requires specialized equipment:

Vector network analyzers: Characterize channel response and impedance for EMC-relevant parameters like return loss and mode conversion.

Real-time oscilloscopes: Capture signal waveforms with sufficient bandwidth (typically 4-5 times the bit rate) to analyze signal quality and jitter.

Bit error rate testers: Measure link reliability under various conditions, including with injected interference.

EMI receivers and spectrum analyzers: Measure radiated and conducted emissions per regulatory and compliance program requirements.

Near-field probes: Locate emission sources on PCBs and within systems for debugging.