Electronics Guide

Piezoelectric Fundamentals

Quartz crystals exhibit the piezoelectric effect, meaning they generate an electric charge when mechanically stressed and conversely deform when an electric field is applied. This bidirectional coupling between mechanical and electrical domains enables the crystal to function as an extremely high-Q resonator. When incorporated into an oscillator circuit, the crystal determines the oscillation frequency with precision impossible to achieve using only resistors, capacitors, and inductors.

The resonant frequency of a crystal depends on its physical dimensions and the orientation at which it was cut from the raw quartz. Different cut angles produce crystals with different temperature characteristics, allowing designers to select the appropriate type for their application. The AT-cut, the most common for electronic applications, offers good temperature stability around room temperature and reasonable performance across the commercial temperature range.

Crystal Oscillator Types

Several categories of crystal oscillators offer different trade-offs between accuracy, stability, power consumption, and cost:

Simple crystal oscillators (XO) provide the most basic implementation, using the crystal with a minimal oscillator circuit. They offer good short-term stability but are subject to frequency variation with temperature. Accuracy specifications typically range from 20 to 100 parts per million (ppm), sufficient for many digital applications but inadequate for precision timing.

Temperature-compensated crystal oscillators (TCXO) add circuitry that senses temperature and applies correction to maintain frequency accuracy across a wide temperature range. By compensating for the crystal's temperature coefficient, TCXOs achieve accuracies of 0.5 to 5 ppm, making them suitable for applications requiring tighter frequency control without the complexity of oven-controlled solutions.

Oven-controlled crystal oscillators (OCXO) maintain the crystal at a constant elevated temperature using a precisely controlled heater. By eliminating temperature variation as a source of frequency error, OCXOs achieve accuracies measured in parts per billion. The trade-off involves higher power consumption for the oven, longer warm-up times, and increased cost.

Voltage-controlled crystal oscillators (VCXO) allow the output frequency to be adjusted by varying an input voltage. This tunability enables phase-locked loops and other frequency synthesis applications while maintaining the inherent stability of crystal-controlled oscillation. The tuning range is typically limited to a few hundred ppm to preserve oscillator performance.

Oscillator Specifications

Understanding key oscillator specifications enables proper selection for specific applications:

• Frequency accuracy: The initial deviation from the nominal frequency, typically specified at 25 degrees Celsius
• Frequency stability: The maximum frequency variation over the operating temperature range
• Aging rate: The long-term drift in frequency, usually specified in ppm per year
• Phase noise: Short-term frequency instability expressed as noise power at various offset frequencies
• Jitter: Cycle-to-cycle timing variations affecting clock edge positions
• Output type: Logic-compatible outputs (CMOS, LVDS, LVPECL) or sinusoidal outputs
• Power consumption: Particularly important for battery-powered applications

Design Considerations

Incorporating crystal oscillators into a design requires attention to several practical factors. Power supply decoupling is essential, as oscillators are sensitive to supply noise that can degrade phase noise performance. Placing decoupling capacitors close to the oscillator power pins filters high-frequency noise that might otherwise modulate the output.

The output signal requires proper termination and routing. Impedance mismatches can cause reflections that distort clock edges and increase jitter. For high-frequency oscillators, treating the output trace as a transmission line with appropriate termination prevents signal integrity problems.

Enable and standby inputs, when present, allow power management by shutting down the oscillator when not needed. However, restarting an oscillator requires a startup time during which the output is invalid. Designs must account for this delay when implementing power-saving features.

PLL Architecture

A basic PLL consists of three essential components connected in a feedback loop. The phase detector compares the reference input to a feedback signal, producing an error signal proportional to their phase difference. The loop filter smooths this error signal, setting the loop bandwidth and stability characteristics. The voltage-controlled oscillator (VCO) generates an output frequency proportional to its input voltage, closing the loop.

When the loop is locked, the VCO output maintains a fixed phase relationship with the reference input. Any phase deviation causes the phase detector to produce an error that adjusts the VCO frequency, pulling the phase back into alignment. This self-correcting behavior creates a stable lock that can track slow variations in the reference while rejecting high-frequency noise.

For frequency synthesis, a frequency divider in the feedback path causes the VCO to oscillate at a multiple of the reference frequency. If the divider ratio is N, the VCO must run at N times the reference frequency to produce the divided-by-N signal that matches the reference. This simple principle enables generation of arbitrarily high frequencies from a stable low-frequency reference.

Integer-N and Fractional-N PLLs

Integer-N PLLs use whole-number division ratios, limiting the achievable output frequencies to integer multiples of the reference. For a 10 MHz reference, the output can be 100 MHz, 110 MHz, 120 MHz, and so on, but not 105 MHz. This quantization constrains frequency planning in systems requiring specific frequencies.

Fractional-N PLLs overcome this limitation by rapidly switching between two or more integer division ratios. The time-averaged division ratio can be any fractional value, enabling fine frequency resolution. A sigma-delta modulator typically controls the divider switching pattern to shape the quantization noise away from frequencies where it would degrade performance.

The choice between integer-N and fractional-N architectures involves trade-offs. Integer-N PLLs offer simpler design and often better spurious performance but limited frequency flexibility. Fractional-N PLLs provide fine frequency resolution at the cost of increased complexity and potential fractional spurs that must be carefully managed.

Loop Bandwidth and Stability

The loop filter design determines the PLL's dynamic behavior, including its bandwidth, stability, and noise characteristics. A wider bandwidth enables faster locking and better tracking of reference frequency variations but passes more reference noise to the output. A narrower bandwidth provides better noise filtering but slower response and potentially stability issues.

Phase margin and gain margin characterize loop stability. Insufficient phase margin causes ringing or oscillation in the loop's transient response. Typical designs target 45 to 60 degrees of phase margin for a well-damped response that settles quickly without excessive overshoot.

The loop bandwidth creates a crossover point in the output phase noise spectrum. At offset frequencies below the bandwidth, the output phase noise follows the reference (multiplied by 20 log N dB due to the division ratio). Above the bandwidth, the VCO's intrinsic phase noise dominates. Proper bandwidth selection balances these contributions for optimal overall performance.

PLL Applications in Digital Systems

PLLs serve numerous functions in digital system design:

• Clock multiplication: Generating high-frequency processor and memory clocks from lower-frequency reference oscillators
• Clock synthesis: Creating multiple unrelated frequencies from a single reference for different system domains
• Clock data recovery: Extracting embedded clock information from serial data streams
• Deskewing: Aligning clock phases to compensate for distribution delays
• Spread spectrum: Modulating clock frequencies to reduce electromagnetic interference peaks
• Jitter attenuation: Filtering input clock jitter through the low-pass characteristic of the loop

PLL Lock Detection and Monitoring

Most PLL implementations include lock detection circuitry that indicates when the loop has achieved and maintains lock. This signal is essential for system bring-up, ensuring that downstream logic does not attempt to operate until valid clocks are available.

Lock detection typically monitors the phase error magnitude or the control voltage range. When the phase error remains small for a specified time, or the control voltage stays within its normal operating range, the lock detector asserts the locked indication. Loss of reference or extreme frequency steps can cause the PLL to lose lock, triggering reset or recovery procedures.

DLL Operating Principles

A DLL consists of a voltage-controlled delay line, a phase detector, and a loop filter. The delay line receives the input clock and produces a delayed version. The phase detector compares this delayed clock to the original input (or a reference derived from it), generating an error signal that adjusts the delay to achieve the desired phase relationship.

In a typical application, the DLL adjusts the delay until the output is exactly one clock period behind the input, effectively aligning the output edges with the input edges. This configuration removes the insertion delay of the clock distribution network, presenting downstream flip-flops with a clock that appears to arrive simultaneously with the source.

Because the DLL does not include a VCO, it cannot generate frequencies different from its input. It also cannot accumulate jitter across multiple clock periods, since each output edge directly derives from an input edge through a fixed delay. This inherent jitter non-accumulation makes DLLs attractive for applications where long-term timing accuracy is critical.

DLL versus PLL Trade-offs

The choice between DLL and PLL depends on the application requirements:

DLLs offer unconditional stability since they lack the feedback oscillator that can cause PLL instability. They do not accumulate jitter and typically achieve faster lock times since the delay range is bounded. However, DLLs cannot multiply frequencies and may have limited delay range that constrains the operating frequency range.

PLLs provide frequency multiplication and wider frequency ranges but require careful design for stability. They can accumulate jitter in the VCO, though proper filtering can minimize this effect. PLLs offer more flexibility in frequency planning and can implement spread spectrum clocking that DLLs cannot provide.

Many modern systems use both: PLLs for frequency synthesis and DLLs for fine phase alignment within the distribution network. This combination leverages the strengths of each architecture where they apply best.

DLL Applications

DLLs find extensive use in memory interfaces, where they align the data strobe with internal clocks to maximize the timing margin for data capture. DDR memory controllers typically include DLLs that track the relationship between the system clock and the memory interface timing.

Clock deskewing applications use DLLs to compensate for asymmetric distribution delays. By measuring the arrival time at different points and adjusting delays accordingly, DLLs can equalize clock edges across large designs where physical distance creates inherent skew.

Duty cycle correction, often integrated with DLL functionality, adjusts the high and low phases of a clock to achieve 50% duty cycle. This correction is important for double-data-rate interfaces where data is captured on both clock edges and requires equal timing margins.

Integrated Clock Generator Features

Modern clock generator ICs typically include:

• Multiple output channels: Generating numerous frequencies simultaneously for different system domains
• Programmable dividers: Setting output frequencies through register configuration
• Multiple PLL cores: Enabling independent frequency synthesis for unrelated clocks
• Output format options: Supporting LVCMOS, LVDS, LVPECL, and other signaling standards
• Spread spectrum capability: Reducing EMI through frequency modulation
• Low-power modes: Shutting down unused outputs to conserve power
• Serial interface: Allowing dynamic reconfiguration through I2C or SPI

Reference Selection and Redundancy

Many clock generators support multiple reference inputs with automatic or manual selection. This capability enables redundant timing architectures where failure of one reference triggers switchover to a backup. The selection logic monitors reference presence and quality, making autonomous decisions about which source to use.

Holdover mode allows the clock generator to maintain its output frequency temporarily when all references fail. The device stores the tuning parameters that achieved lock and continues generating output at the last known good frequency. While accuracy degrades over time without a reference, holdover provides continuity for systems that cannot tolerate immediate clock failure.

Jitter Performance Considerations

Clock generator jitter specifications warrant careful attention because they directly impact the timing margin available for data capture. Jitter adds uncertainty to clock edge positions, reducing the effective setup and hold time windows for flip-flops.

Random jitter accumulates statistically and is typically specified as an RMS value. Deterministic jitter, caused by systematic effects like power supply coupling or crosstalk, adds a bounded amount to each edge. The combination of these components determines the total jitter budget that must be accommodated in timing analysis.

Different applications have different jitter sensitivities. High-speed serial links require extremely low jitter because the data eye closes rapidly at gigabit rates. General-purpose digital logic tolerates more jitter since operating frequencies are lower and timing margins are larger. Selecting a clock generator with appropriate jitter performance avoids both over-specifying (wasting cost) and under-specifying (risking failures).

Buffer Topologies

Clock buffers come in several configurations to address different distribution requirements:

Fan-out buffers take a single input and produce multiple outputs, each capable of driving its own branch of the distribution tree. The outputs typically have matched delays to minimize skew between branches. Common fan-out ratios range from 1:2 to 1:12 or more.

Zero-delay buffers incorporate a PLL or DLL that aligns the output with the input, compensating for the buffer's internal delay. This alignment ensures that downstream clocks maintain a known phase relationship with the source despite distribution delays.

Level-translating buffers convert between signaling standards, enabling connection between components using different voltage levels or differential formats. A buffer might accept LVDS input and produce LVCMOS outputs, for example.

Clock Tree Synthesis

In integrated circuits and FPGAs, clock tree synthesis (CTS) is the automated process of creating the buffer network that distributes clocks from sources to sequential elements. The goal is to minimize skew (the variation in clock arrival times) while meeting other constraints on power, area, and timing.

Traditional H-tree structures divide the chip into progressively smaller regions, with buffers at each branch point. This geometric approach naturally balances delays to all destinations. Modern CTS algorithms use more sophisticated techniques that consider the actual placement of flip-flops, creating non-uniform trees that achieve lower skew than regular geometric patterns.

Clock tree optimization continues after initial synthesis, adjusting buffer sizes and positions to meet timing requirements identified by post-CTS analysis. This iterative refinement converges on a solution that satisfies all constraints while minimizing power consumption and area overhead.

Skew Management

Clock skew directly impacts timing margins for both setup and hold. Excessive skew in one direction steals time from setup margins; in the other direction, it threatens hold times. Managing skew requires understanding its sources and applying appropriate countermeasures.

Sources of skew include buffer delay variations, interconnect length differences, loading imbalances, and environmental variations (temperature, voltage) that affect different parts of the design differently. Process variations during manufacturing also contribute, as nominally identical buffers may have slightly different delays.

Techniques for managing skew include balanced tree structures, useful skew insertion (intentionally adding delay where it helps timing), clock mesh architectures that average out local variations, and post-silicon tuning options that adjust delays after manufacturing.

Signal Integrity in Clock Distribution

At high frequencies, clock distribution traces behave as transmission lines. Reflections from impedance discontinuities create waveform distortions that can cause double clocking or marginal edge detection. Proper termination strategies match the line impedance to prevent reflections.

Source termination places a resistor at the driver output, matched to the line impedance. The incident wave travels along the line at half amplitude, reflects fully at the open end, and returns to create a full-amplitude step at the driver. This approach works well for point-to-point connections but requires time for the reflection to complete.

End termination places a matched load at the destination, absorbing the incident wave without reflection. This provides clean waveforms immediately but requires steady-state current flow that increases power consumption. Various hybrid schemes balance these trade-offs for specific applications.

Tree Architecture Fundamentals

A clock tree begins at the root, typically the output of a PLL or clock buffer, and branches repeatedly until every flip-flop receives its clock input. Each branching level adds buffers that amplify the signal and drive the next level of fanout. The depth of the tree (number of buffer stages) balances the trade-off between buffer delay and the capacitive load each buffer must drive.

The insertion delay of a clock tree is the time from the root to the most distant leaf. This delay must be accounted for in timing analysis but does not itself cause timing problems as long as it is consistent across the design. Variation in insertion delay across different paths creates skew, which is the critical parameter to minimize.

Clock tree power consumption can represent a significant fraction of total chip power, as every clock edge charges and discharges all the capacitance in the tree. Reducing tree capacitance through careful buffer sizing and wire routing directly reduces dynamic power. Clock gating provides further power savings by stopping clock activity in unused portions of the design.

Symmetric versus Asymmetric Trees

Symmetric trees use identical structures for each branch, creating uniform delays to all destinations. The classic H-tree exemplifies this approach, with recursive division of the chip area into identical quadrants. Symmetric trees are easy to analyze and provide naturally balanced delays.

Asymmetric trees adapt their structure to the actual distribution of flip-flops, which is rarely uniform across a design. Placing buffers and sizing them according to actual loads can achieve lower skew than a symmetric tree would provide. Modern synthesis tools create these optimized structures automatically based on placed cell locations.

The choice between symmetric and asymmetric approaches involves trade-offs. Symmetric trees are more predictable during early design stages before placement is complete. Asymmetric trees achieve better results but require iterative optimization as placement evolves. Most modern flows use asymmetric approaches with the flexibility to handle placement changes.

Clock Mesh Structures

An alternative to tree structures, clock meshes distribute clocks through a grid of interconnected wires driven from multiple points. The mesh averages out local delay variations, providing inherently low skew at the cost of higher power consumption due to the redundant paths.

Mesh architectures find favor in very high-performance processors where minimum skew justifies the power penalty. The grid structure also provides tolerance to manufacturing defects, as multiple paths exist to every destination. If one path is defective, others continue to deliver the clock.

Hybrid approaches combine tree structures for initial distribution with local meshes for fine-grained skew control. The tree delivers clocks to regions of the chip, where meshes ensure minimal skew within each region. This combination captures benefits of both approaches while limiting the power overhead of full-chip meshes.

Gating Principles and Implementation

The basic clock gating cell combines a clock input with an enable signal to produce a gated clock output. When enable is active, the clock passes through normally. When enable is inactive, the output remains static, preventing clock transitions from reaching downstream flip-flops.

Simple AND-gate gating risks glitches if the enable signal changes while the clock is high. Integrated clock gating (ICG) cells solve this by using a latch to hold the enable value until the clock goes low, ensuring clean transitions. This latch-based approach is standard in modern designs and typically implemented as a specialized library cell optimized for this function.

The granularity of clock gating involves trade-offs. Fine-grained gating of individual registers provides maximum power savings but requires many gating cells with their associated area and timing overhead. Coarse-grained gating of entire blocks uses fewer cells but may gate regions that still need clocks for some operations.

Automatic Clock Gating Insertion

Modern synthesis tools automatically insert clock gating by analyzing register enable patterns. When a register has an enable term that can be factored out to control the clock rather than a data multiplexer, the tool replaces the multiplexer with a gating cell. This transformation preserves functionality while reducing power.

Synthesis directives guide the automatic insertion process. Designers can specify minimum bit counts for gating (ensuring the power savings justify the overhead), prevent gating of certain registers (for functional or timing reasons), and control the gating structure for specific portions of the design.

Verification of clock gating correctness is essential, as errors can cause functional failures. Formal verification and simulation techniques confirm that gated clocks activate whenever data transactions require them. Coverage metrics track gating activity to identify opportunities for additional power savings.

Multi-Level Clock Gating

Hierarchical gating strategies combine multiple levels of control for maximum efficiency. At the highest level, entire functional blocks can be gated when not in use. Within active blocks, finer-grained gating controls individual registers or small groups.

Activity analysis drives the gating hierarchy design. Understanding which portions of the design are active together enables grouping them under common gating control. Portions that frequently activate and deactivate independently benefit from separate gating.

The timing impact of clock gating requires attention. Gating cells add latency to the clock path, affecting insertion delay. They also add potential for skew if different gating conditions create different path delays. Timing analysis must account for both enabled and disabled states of each gating cell.

Understanding the CDC Problem

When a signal crosses between clock domains, the receiving flip-flop may sample it at any point relative to the transmitting flip-flop's clock edge. If the sample occurs during or immediately after a transition, the receiving flip-flop may violate setup or hold times, entering a metastable state where the output is neither valid high nor valid low.

Metastability eventually resolves to a valid state, but the resolution time is probabilistic. Downstream logic that uses the metastable output before it resolves may propagate invalid values through the system, causing functional failures. These failures are probabilistic and may occur rarely, making them extremely difficult to diagnose through conventional testing.

The frequency relationship between domains affects CDC behavior. Synchronous domains with related frequencies (sharing a common reference) have predictable phase relationships that can be exploited. Asynchronous domains with unrelated frequencies have fully random phase relationships, requiring robust synchronization for all crossings.

Single-Bit Synchronization

For single-bit signals crossing between domains, synchronizer flip-flops provide the basic solution. Two or more flip-flops in series, clocked by the receiving domain clock, give metastable states time to resolve before affecting downstream logic.

The first flip-flop may enter metastability when sampling a changing input. The second flip-flop samples the first flip-flop's output after it has had nearly one clock period to resolve. With proper design, the probability of metastability persisting through both stages becomes negligibly small.

Three-stage synchronizers provide additional margin in high-reliability applications or when operating frequencies are very high. Each additional stage exponentially increases the mean time between failures (MTBF), though it also adds latency to the crossing.

Synchronizer design requires careful attention to timing. The flip-flops should be placed close together to minimize interconnect delay that would reduce resolution time. Special low-jitter flip-flop cells optimized for synchronizer use may be available in the cell library.

Multi-Bit Crossing Techniques

Crossing multiple bits simultaneously presents additional challenges because each bit may resolve differently, creating inconsistent values in the receiving domain. Several techniques address this problem:

Gray coding ensures that only one bit changes between adjacent values. When a multi-bit counter crosses domains using Gray code, any sampling instant captures a valid code, even if it represents either the old or new value. This technique is fundamental to asynchronous FIFO design.

Handshaking protocols exchange control signals between domains to coordinate data transfers. The transmitting domain asserts a request, the receiving domain synchronizes this request and acknowledges after capturing data, and the transmit domain synchronizes the acknowledgment before proceeding. This exchange ensures data stability during capture at the cost of increased latency.

Asynchronous FIFOs buffer data between domains, decoupling their timing. Write and read pointers maintained in their respective domains use Gray-coded crossing to check for full and empty conditions. The FIFO depth accommodates timing variations between write and read rates.

CDC Verification

Verifying correct clock domain crossing handling requires specialized techniques beyond standard functional verification. Simulation alone is inadequate because metastability effects are probabilistic and may not occur during any finite simulation time.

Formal CDC verification tools analyze the design structurally to identify all signals that cross between domains. They flag crossings without proper synchronization, multi-bit crossings that could create inconsistent values, and reconvergent paths where separately synchronized signals recombine.

Protocol checking verifies that handshaking sequences follow correct ordering and timing. This verification ensures that data is stable when sampled and that no signals are missed or duplicated during transfers.

Types of Jitter

Jitter is categorized by its characteristics and sources:

Random jitter (RJ) arises from fundamental noise sources like thermal noise and shot noise. Its distribution is Gaussian, meaning occasional large deviations occur with probability determined by the standard deviation. Random jitter is typically specified as an RMS value that characterizes the Gaussian distribution.

Deterministic jitter (DJ) is bounded and repeatable, caused by systematic effects in the clock path. Subcategories include periodic jitter (correlated with clock frequency or subharmonics), data-dependent jitter (correlated with switching patterns), and duty-cycle distortion (asymmetry between high and low phases).

Total jitter (TJ) combines random and deterministic components. For a given bit error rate (BER), total jitter is calculated from the deterministic jitter plus a multiple of the random jitter RMS value (the multiplier depends on the target BER).

Jitter Measurement and Specification

Jitter can be measured and specified in several ways, each appropriate for different analyses:

Period jitter measures the variation in clock period from cycle to cycle. This specification is most relevant for logic timing analysis, where the effective clock period may be shorter than nominal due to jitter.

Cycle-to-cycle jitter measures the change in period between adjacent cycles. Large cycle-to-cycle jitter can stress clock recovery circuits and cause problems in phase-locked systems.

Phase jitter measures accumulated timing deviation over many cycles, relevant for applications like data converters where long-term timing accuracy affects performance.

Time interval error (TIE) measures the deviation of each edge from an ideal reference. TIE captures both random and deterministic components in a single measurement.

Jitter Budgeting

System-level jitter analysis allocates the total allowable jitter among various sources. The crystal oscillator contributes its phase noise. The PLL adds its own noise while filtering some oscillator noise. The distribution network introduces jitter from crosstalk and power supply variations. Finally, the receiving flip-flop has input sensitivity that determines how much jitter can be tolerated.

Root-sum-square (RSS) combination of uncorrelated jitter sources gives the total expected jitter. This statistical combination is valid for random components but may underestimate the total if significant correlated deterministic jitter exists.

Timing analysis tools accept jitter specifications as constraints, adding jitter to setup and hold time calculations. The jitter budget must leave sufficient margin for worst-case timing after accounting for all sources of uncertainty.

Reducing Jitter

Several techniques minimize jitter in clock systems:

• Power supply filtering: Clean, well-decoupled supplies reduce coupling of supply noise onto clock signals
• Ground plane design: Solid ground planes minimize return path inductance that can cause jitter
• Isolation: Physical and electrical separation of clock circuits from noisy digital logic reduces coupling
• Component selection: Low-jitter oscillators and buffers establish a solid foundation
• Termination: Proper transmission line termination prevents reflections that cause jitter
• Loop bandwidth optimization: PLL and DLL bandwidth selection balances filtering and tracking

Clock Planning

Early attention to clock architecture prevents problems later in the design cycle. Key considerations include:

• Identify all clock domains and their frequency relationships
• Determine which domains require synchronous relationships and which are truly asynchronous
• Plan clock generation and synthesis to minimize the number of independent oscillators
• Identify all clock domain crossings and specify appropriate synchronization methods
• Establish jitter budgets for each timing-critical interface
• Plan power management modes and their impact on clock availability

Layout and Routing Considerations

Physical implementation of clock networks requires attention to signal integrity:

• Route clock signals on inner layers, shielded by ground planes
• Maintain consistent impedance along clock traces
• Avoid routing clocks near high-speed switching signals
• Place clock generators and buffers with adequate power supply decoupling
• Match trace lengths for signals requiring matched timing
• Consider thermal effects on oscillator and buffer performance

Verification and Testing

Thorough verification ensures clock system reliability:

• Verify PLL lock time and stability across all operating conditions
• Measure clock jitter at key points in the distribution network
• Confirm clock domain crossing synchronizers through formal verification
• Validate clock gating correctness through simulation and formal methods
• Test clock recovery from power-down and reset conditions
• Stress test timing margins across temperature and voltage variations