Electronics Guide

Stuck-At Fault Testing

Testing for stuck-at faults requires two fundamental conditions: fault activation and fault propagation. Activation means applying input values that would cause a difference between the fault-free and faulty circuit at the fault site. Propagation means ensuring that this difference reaches a primary output where it can be observed.

Consider a two-input AND gate where the first input is suspected of being stuck-at-0. To test this fault, the test must first activate it by applying a logic 1 to that input (which would produce a different result if the node were actually stuck-at-0). The test must then propagate the effect by setting the second input to logic 1, allowing the output to reflect the first input's value. If the fault exists, the output will be 0 instead of the expected 1.

For complex circuits, finding patterns that simultaneously activate faults and propagate their effects through multiple levels of logic becomes challenging. This motivates the development of automatic test pattern generation algorithms discussed later in this article.

Transition Fault Testing

Transition faults model timing defects where a signal line fails to change state within the required time window. A slow-to-rise fault means the signal cannot transition from 0 to 1 quickly enough, while a slow-to-fall fault indicates inability to transition from 1 to 0 in time. These faults capture many real defects including resistive opens, weak transistors, and increased parasitic capacitance.

Testing transition faults requires two patterns applied in sequence. The first pattern initializes the fault site to the appropriate starting value. The second pattern launches a transition at the fault site and propagates the result to an output. The time between patterns determines what delay magnitude can be detected. At-speed testing applies the second pattern at the operational clock frequency, catching faults that would cause functional failures at normal operating speeds.

Two main approaches launch transitions for at-speed testing. Launch-on-shift uses the final shift operation of a scan chain to create the transition, while launch-on-capture uses a functional clock pulse. Launch-on-capture more accurately represents functional timing but requires careful clock control and can be more complex to implement.

Path Delay Testing

Path delay testing targets the cumulative delay along specific signal paths from primary inputs or registers to primary outputs or registers. A path delay fault exists when the total delay along a path exceeds the clock period minus required setup time. This comprehensive approach tests actual timing behavior rather than individual gate delays.

The challenge with path delay testing is the astronomical number of potential paths in complex circuits. A circuit may contain more paths than can be enumerated, let alone tested. Practical path delay testing therefore focuses on critical paths identified by timing analysis and on paths likely to be affected by manufacturing variations.

Robust path delay testing requires that a test sensitize a single path without ambiguity. A robustly testable path has the property that the test pattern guarantees propagation along exactly the intended path regardless of other circuit delays. Non-robust tests may produce incorrect pass or fail results if delays along unintended paths interact with the test.

Small Delay Defect Testing

Traditional delay testing targets defects causing delays larger than the timing slack on tested paths. However, manufacturing defects can cause smaller delays that pass timing requirements under typical conditions but cause failures under process, voltage, or temperature variations. Small delay defect testing aims to detect these latent reliability risks.

Several techniques address small delay defects. Testing at reduced voltage increases all circuit delays, effectively amplifying small delay defects until they cause timing failures. Testing at higher than nominal frequency similarly tightens timing margins to expose marginal paths. Statistical timing analysis can identify paths with reduced delay margin due to multiple small delay defects.

IDDQ Test Implementation

Practical IDDQ testing requires careful consideration of measurement setup and current thresholds. The current must be measured after all switching activity has ceased and the circuit has reached steady state. Sensitive current measurement equipment must distinguish defect current from background leakage, which increases with device complexity and temperature.

Modern deep submicron technologies present challenges for IDDQ testing due to increased transistor leakage currents. In earlier technologies, defect-free quiescent currents were in the nanoampere range, making microampere defect currents easy to detect. Current technologies may have milliampere-level background leakage, reducing the ratio between defective and defect-free currents.

Despite these challenges, IDDQ testing remains valuable for detecting certain defect classes. Delta-IDDQ techniques measure current differences between test patterns rather than absolute values, improving sensitivity by canceling background leakage. Built-in current sensors can be integrated on-chip to avoid external measurement limitations. IDDQ testing is particularly effective during reliability screening to identify devices likely to fail during operation.

Defect Coverage Considerations

IDDQ testing detects defects that create DC paths between power and ground. This includes bridging faults between nodes at different logic levels, gate oxide defects that short gate to source or drain, and some types of stuck-open faults where transistor subthreshold leakage becomes measurable. IDDQ cannot detect defects that do not create leakage paths, such as clean stuck-at faults or timing-only defects.

The value of IDDQ testing lies in its ability to catch defects that might pass logical tests but cause reliability problems. A resistive bridge might still allow correct logic levels while creating a current path. Such defects may work initially but fail over time as electromigration or other wear-out mechanisms progress. IDDQ screening can eliminate these latent defects before they reach customers.

Boundary Scan Architecture

Each boundary scan compatible device includes a test access port (TAP) with four or five dedicated pins: test clock (TCK), test mode select (TMS), test data input (TDI), test data output (TDO), and an optional test reset (TRST). These pins provide a serial interface for controlling test operations and shifting data through the device.

The boundary scan register is a shift register with one cell associated with each I/O pin of the device. During normal operation, the boundary scan cells are transparent, passing signals directly between the core logic and I/O pins. During test mode, the boundary scan register can capture the state of all pins, shift data through the register serially, and drive pin values independent of the core logic.

Multiple boundary scan devices connect in a daisy chain, with TDO of one device connected to TDI of the next. A single TAP interface can therefore access the boundary scan registers of all devices on a board. The test controller shifts patterns through the entire chain, enabling comprehensive board-level testing through minimal physical access points.

Test Operations

Boundary scan supports several fundamental test operations. The EXTEST instruction captures input pin values and drives output pin values from the boundary scan register, enabling testing of board interconnections between devices. The SAMPLE instruction captures input values while the device operates normally, useful for debugging and monitoring.

The INTEST instruction tests the internal logic of a device by driving its inputs from and capturing its outputs to the boundary scan register. This effectively provides controllability and observability for internal testing without requiring scan chains in the core logic. The BYPASS instruction places a single-bit register in the scan path, minimizing shift time when testing does not require access to a particular device's boundary register.

Manufacturers often implement optional instructions extending basic boundary scan capability. The IDCODE instruction retrieves a device identification register, useful for verifying correct component placement and version. The USERCODE instruction accesses a user-programmable register for application-specific purposes. Device-specific instructions may provide access to built-in self-test functions, on-chip debug capabilities, or in-system programming.

System Applications

Beyond board interconnection testing, boundary scan has evolved into a versatile infrastructure for system development and maintenance. In-system programming uses boundary scan to download configuration data to FPGAs and flash memories without removing devices from the board. Debug interfaces like ARM CoreSight and MIPS EJTAG build on the JTAG physical layer to provide processor debug and trace capabilities.

IEEE 1149.6 extends boundary scan to high-speed differential and AC-coupled interconnections common in modern communication interfaces. IEEE 1687 (IJTAG) provides a standardized method for accessing embedded instruments within devices through the JTAG interface. These extensions maintain backward compatibility while addressing the evolving needs of complex electronic systems.

Scan Flip-Flop Architecture

A scan flip-flop includes a multiplexer at its data input, selecting between the normal functional data and the scan data input based on a scan enable signal. During normal operation, the multiplexer selects functional data, and the flip-flop operates normally within the design. During scan mode, the multiplexer selects data from the previous flip-flop in the scan chain, forming a shift register.

Several scan flip-flop variants exist with different trade-offs. Multiplexed scan adds a two-input multiplexer to a standard flip-flop, incurring area and timing overhead. Level-sensitive scan design (LSSD) uses a dual-latch structure with overlapping clock phases, providing robust race-free operation at the cost of increased area. Enhanced scan adds a holding latch, enabling two-pattern delay testing at additional overhead.

Scan Chain Organization

A full-scan design connects all flip-flops into one or more scan chains. With all state elements accessible, the sequential circuit becomes a combinational circuit between scan operations, dramatically simplifying test generation. Stuck-at fault coverage exceeding 95% is routinely achievable with automatic test pattern generation on full-scan designs.

Large designs partition flip-flops into multiple scan chains that can be loaded and unloaded simultaneously, reducing test time. The number of scan chains balances test time against the I/O pin count dedicated to scan access. Modern designs may include hundreds of scan chains, each containing thousands of flip-flops.

Scan chain ordering affects test quality and debug capability. Ordering flip-flops by physical location minimizes scan chain wire length and simplifies scan chain routing. Ordering by functional grouping can aid in diagnosis when failures occur. Some designs use multiple independently controllable scan chains for flexible test configuration.

Partial Scan and Trade-Offs

While full scan provides maximum testability, it incurs area, power, and performance penalties. Each scan flip-flop is larger than its non-scan equivalent. The scan chain routing consumes wiring resources. The scan multiplexer adds delay in the functional data path. Power consumption increases due to additional clock loading and scan chain switching during test.

Partial scan designs include scan capability on only a subset of flip-flops, typically selected to break feedback loops and reduce sequential depth. Partial scan achieves significant testability improvement with reduced overhead but requires more sophisticated test generation that considers both scannable and non-scannable state elements. Careful selection of which flip-flops to scan maximizes testability benefit per unit of overhead.

D-Algorithm and Path Sensitization

The D-algorithm, introduced by Roth in 1966, formalized the concept of path sensitization for stuck-at fault test generation. The algorithm represents circuit values using a five-valued logic: 0, 1, X (unknown), D (1 in the fault-free circuit, 0 in the faulty circuit), and D' (0 in the fault-free circuit, 1 in the faulty circuit). D and D' represent the fault effect that must propagate to an observable output.

The D-algorithm operates in two phases. The forward phase propagates the fault effect from the fault site toward primary outputs, selecting gates that will transmit the D or D' value. The backward phase justifies the required input values by tracing backward from internal nodes to primary inputs. When both phases complete successfully, the algorithm has found a valid test pattern.

Conflicts arise when requirements for sensitization and justification are incompatible. When a conflict occurs, the algorithm backtracks to try alternative choices. Effective backtracking strategies and conflict-driven learning dramatically impact algorithm efficiency on complex circuits.

PODEM and FAN Algorithms

PODEM (Path-Oriented Decision Making) improved upon the D-algorithm by focusing decisions on primary inputs rather than internal nodes. By making decisions only at primary inputs and propagating their effects forward, PODEM achieves a more systematic search with better backtracking properties. The algorithm evaluates the effect of each primary input decision on the objectives of fault activation and propagation.

FAN (Fanout-Oriented Test Generation) further improved efficiency through multiple backtrack points and fanout analysis. Rather than backtracking to the most recent decision, FAN can identify which decision caused the conflict and backtrack directly to that point. FAN also handles fanout structures more efficiently, reducing redundant work when multiple paths reconverge.

Modern ATPG Techniques

Contemporary ATPG tools incorporate many enhancements beyond classical algorithms. Boolean satisfiability (SAT) solvers provide powerful engines for resolving complex test generation problems. Learning records successful and unsuccessful assignments to avoid repeating failed attempts. Parallel ATPG distributes fault processing across multiple processors for faster generation.

Fault simulation complements test generation by evaluating how many faults each pattern detects. After generating a pattern for a target fault, fault simulation identifies all other faults that the pattern also detects. This fault dropping accelerates ATPG by eliminating faults that need not be explicitly targeted. Dynamic compaction generates patterns that detect multiple targeted faults simultaneously, reducing pattern count.

Serial and Parallel Fault Simulation

Serial fault simulation simulates each fault individually, comparing the faulty circuit response against the fault-free response for each test pattern. While straightforward, this approach requires circuit simulations proportional to the product of fault count and pattern count, becoming impractical for large designs.

Parallel fault simulation exploits the bitwise nature of logic operations to simulate multiple faults simultaneously. By packing different fault scenarios into the bits of computer words, a single logic operation processes many faults in parallel. With 64-bit words, parallel fault simulation achieves up to 64x speedup over serial simulation, though practical gains depend on the circuit structure and fault distribution.

Concurrent Fault Simulation

Concurrent fault simulation maintains separate representations only for gates that behave differently under each fault. Most faults affect only a small portion of the circuit at any time, so concurrent simulation stores and processes only the differences from fault-free behavior. Event-driven simulation updates only gates whose inputs have changed.

The data structures for concurrent simulation can be complex, tracking which faults have diverged from fault-free behavior at each gate. Memory requirements scale with the number of faults exhibiting different behavior rather than total faults. For circuits with many faults but limited fault propagation, concurrent simulation achieves dramatic efficiency improvements.

Fault Coverage Metrics

Fault coverage, the percentage of modeled faults detected by a test set, serves as the primary test quality metric. However, raw coverage numbers require careful interpretation. Redundant faults cannot be detected by any test because the fault effect cannot propagate to an output. Untestable faults may be blocked by test constraints such as limited clock control. Aborted faults could not be simulated completely due to memory or time limits.

Effective fault coverage accounts for these categories, computing the ratio of detected faults to potentially detectable faults. Coverage of 98% on all faults might correspond to 99.5% effective coverage when redundant and untestable faults are excluded. Understanding these distinctions is essential for meaningful quality comparisons and test improvement prioritization.

Test Stimulus Compression

Test stimulus compression exploits the fact that most bits in uncompressed test patterns are "don't care" values. ATPG specifies only those bits essential for fault detection, leaving many scan cells with arbitrary values. Compression schemes encode only the specified bits, expanding them on-chip to fill the complete scan chains.

Linear decompressors use networks of XOR gates to expand a small number of compressed input bits into a large number of scan chain inputs. The decompressor typically consists of a linear feedback shift register (LFSR) combined with a combinational phase-shifting network. Each compressed bit influences many scan cells, but the linear structure ensures that any sparse pattern of specified bits can be achieved by appropriate compressed input.

Broadcasting shifts identical data into multiple scan chains simultaneously, achieving compression when the same value is needed in corresponding positions across chains. Combined with linear expansion, broadcasting can achieve compression ratios exceeding 100x, meaning test data volume is reduced to less than 1% of the uncompressed size.

Response Compaction

Response compaction reduces the volume of test output data by compressing scan chain outputs on-chip before observation. The most common approach uses multiple-input signature registers (MISRs) that combine all scan outputs into a single signature value. After each test pattern, the MISR accumulates the scan output values. At the end of testing, the final signature is compared against the expected value for a fault-free device.

Compaction introduces the possibility of aliasing, where a faulty response produces the same signature as a fault-free response. Proper MISR design minimizes aliasing probability to negligible levels. For typical configurations, aliasing probability is less than one in billions of faults, far below the natural defect rate of manufacturing processes.

The primary challenge with response compaction is handling unknown (X) values in scan outputs. An X value entering a MISR propagates and eventually corrupts the entire signature, preventing pass or fail determination. X-tolerance techniques either block X values from entering the compactor or use compactor architectures that limit X propagation. Managing X values is often the most complex aspect of compression implementation.

Embedded Compression Architectures

Commercial compression solutions integrate stimulus decompression and response compaction into unified architectures. These embedded compression schemes are inserted between the scan chains and primary I/O, typically as part of the design-for-test insertion flow. The compression hardware operates transparently, accepting compressed patterns from the tester and returning compacted responses.

Leading embedded compression products achieve compression ratios of 100x or more while maintaining near-complete fault coverage. The on-chip compression hardware adds modest area overhead, typically less than 1% of chip area, but dramatically reduces test time and test data storage requirements. For large designs, compression can reduce test costs by millions of dollars over product lifetime.

Logic BIST

Logic BIST generates pseudo-random patterns using on-chip hardware, typically a linear feedback shift register (LFSR). The LFSR cycles through a pseudo-random sequence of values that are applied to the circuit under test through the scan chains. Output responses are compacted by a MISR to produce a signature that indicates pass or fail.

The primary challenge with logic BIST is achieving adequate fault coverage with random patterns. Some faults are random-pattern resistant, requiring specific input combinations that pseudo-random sequences are unlikely to generate. Solutions include modifying the LFSR sequence with weighted random patterns, inserting test points that improve random pattern testability, or storing deterministic patterns for resistant faults.

Memory BIST

Memory BIST is nearly universal in modern designs due to the specific characteristics of memory testing. Memories require repetitive patterns applied in systematic address sequences to detect cell faults, coupling faults, and address decoder faults. On-chip memory BIST controllers implement standard march algorithms like March C- more efficiently than external testers could manage.

Memory BIST also enables repair of defective memory cells using redundant rows and columns. The BIST controller identifies failing addresses, which are compared against available redundancy resources. Fuse or antifuse elements program the memory to substitute redundant cells for defective ones, improving yield significantly for large memories.

Test Point Insertion

Test points are additional hardware elements inserted specifically to improve testability. Observation points add flip-flops that capture internal signal values, making otherwise unobservable signals visible. Control points add multiplexers that allow direct control of internal signals during test mode.

Automated test point insertion analyzes fault coverage limitations and inserts test points to improve coverage of resistant faults. The trade-off is area and timing overhead against coverage improvement. Effective algorithms identify minimal test point sets that achieve coverage targets while minimizing impact on circuit performance.

Clock Control

Complex clock structures challenge test implementation. Multiple asynchronous clock domains, gated clocks, and derived clocks must all be controlled precisely during testing. DFT techniques include clock bypassing to provide controllable test clocks, clock domain synchronization structures, and on-chip clock controllers that sequence clock operations during test.

At-speed testing requires launching and capturing at functional frequencies, demanding careful clock control. Transition testing uses precisely timed clock pulses to launch transitions and capture results. PLL bypassing or on-chip test clocks provide the required timing control while maintaining meaningful correlation to functional timing.