Electronics Guide

Historical Node Naming

In early semiconductor manufacturing, node names corresponded directly to measurable physical features. The gate length of transistors served as the primary metric, with process generations identified by this dimension. A 1-micrometer (1000 nm) process used transistors with approximately 1-micrometer gate lengths, and the name accurately reflected the physical reality.

This straightforward naming continued through the sub-micrometer era. Nodes at 800 nm, 600 nm, 350 nm, 250 nm, 180 nm, 130 nm, and 90 nm generally maintained reasonable correspondence between the node name and actual transistor dimensions. Industry roadmaps such as those published by the Semiconductor Industry Association (SIA) and later the International Technology Roadmap for Semiconductors (ITRS) used these designations to coordinate industry development efforts.

The relationship between node names and physical dimensions began to diverge around the 65 nm and 45 nm generations. Manufacturing challenges and the introduction of strain engineering, high-k dielectrics, and metal gates meant that transistor dimensions no longer scaled uniformly. Different foundries defined nodes differently, and marketing considerations began influencing nomenclature.

Modern Node Naming Complexity

Contemporary node names bear only loose relationship to any single physical dimension. A "7 nm" process from one foundry may have transistor dimensions similar to a "10 nm" process from another. The industry has effectively adopted node names as branding rather than precise technical specifications.

Several factors contribute to this naming complexity:

• Gate pitch: The center-to-center spacing between adjacent gates, often around 50-60 nm at the "7 nm" node
• Metal pitch: The minimum metal line spacing, typically larger than the node name suggests
• Fin pitch: For FinFET processes, the spacing between fins, another relevant dimension
• Contacted poly pitch: Sometimes used as a reference dimension
• Density metrics: Transistors per square millimeter provide process-independent comparison

The absence of a standardized definition means designers must look beyond node names to understand actual process capabilities. Foundry datasheets, design rule manuals, and transistor characterization data provide the concrete specifications needed for design decisions.

Industry Efforts at Standardization

Recognizing the confusion caused by inconsistent naming, industry organizations have attempted to establish clearer metrics. The IEEE proposed using logic transistor density (millions of transistors per square millimeter) as a more objective comparison. This approach measures what ultimately matters for digital logic: how many transistors fit in a given area.

Some analysis now references "equivalent node" concepts that normalize different foundries' processes to comparable capability levels. These efforts help customers compare options more accurately, though proprietary node names remain dominant in marketing materials.

The transition to gate-all-around (GAA) transistors and other novel structures will likely prompt further naming evolution. Some manufacturers have adopted "angstrom" designations (such as "A7" or "2A") for upcoming nodes, signaling a shift in naming conventions as physical scaling continues.

Planar Transistor Geometry

Traditional planar transistors, used through approximately the 22-28 nm generation, feature a gate electrode sitting atop a thin gate oxide over a silicon channel. The key dimensions include:

Gate length: The distance between source and drain regions, determining how quickly carriers transit the channel. Shorter gates enable faster switching but increase short-channel effects that degrade performance. Early nodes named processes after this dimension.

Gate oxide thickness: The insulating layer between the gate and channel, traditionally silicon dioxide. Thinner oxides provide better gate control but increase leakage current. At the 65 nm node and below, high-k dielectrics replaced silicon dioxide to maintain gate control with acceptable leakage.

Channel width: The transistor dimension perpendicular to current flow, determining drive current capability. Wider transistors provide more current but consume more area. Designers choose width based on performance requirements.

Junction depth: How deeply the source and drain regions extend into the silicon, affecting both resistance and short-channel behavior. Shallow junctions improve electrostatic control but increase parasitic resistance.

FinFET Dimensions

FinFET transistors, introduced at the 22 nm (Intel) and 16/14 nm (foundry) nodes, revolutionized transistor structure by using vertical fins of silicon wrapped by the gate. This three-dimensional structure provides superior electrostatic control compared to planar devices.

Key FinFET dimensions include:

• Fin height: The vertical extent of the silicon fin, typically 40-50 nm in modern processes
• Fin width: The thickness of the fin at its narrowest point, often 6-8 nm at advanced nodes
• Fin pitch: The center-to-center spacing between adjacent fins, typically 25-35 nm
• Gate length: Still relevant, though now wrapping around the fin in three dimensions
• Number of fins: Multiple fins in parallel provide higher drive current

FinFET design introduces quantization effects absent in planar transistors. Drive strength comes in discrete increments based on the number of fins, rather than the continuous width adjustment available with planar devices. This quantization affects circuit design, particularly for analog and mixed-signal functions.

Gate-All-Around Transistors

Gate-all-around (GAA) transistors, also known as nanosheet or nanowire transistors, represent the next evolution in transistor structure. These devices stack horizontal sheets or wires of silicon with the gate material completely surrounding each channel. Samsung and Intel have begun production with GAA structures at their most advanced nodes.

GAA dimensions include:

• Sheet/wire width: The lateral extent of each channel element
• Sheet/wire thickness: The vertical dimension of each channel
• Number of sheets: Stacking more sheets provides higher drive current
• Vertical spacing: The gap between stacked sheets

GAA structures offer improved electrostatic control compared to FinFETs, essential for continued scaling. The ability to tune sheet width provides some of the continuous sizing flexibility lost with FinFET's fin quantization, though device design remains more complex than planar transistors.

Metal Stack Evolution

Early integrated circuits used aluminum interconnects with silicon dioxide insulation. This combination served the industry well through the 180 nm node. Beginning at 130 nm and 90 nm, copper replaced aluminum as the primary conductor, offering lower resistance that became critical as wire cross-sections shrank.

The transition to copper required new manufacturing approaches. Unlike aluminum, copper cannot be dry-etched with acceptable precision. The damascene process, where copper fills pre-etched trenches in the dielectric, became the standard manufacturing method. Barrier and seed layers prevent copper diffusion into the silicon and enable electroplating.

Modern processes use 10-15 metal layers to route signals, power, and ground across complex chips. Lower layers with fine pitch handle local routing between nearby transistors. Upper layers with larger dimensions carry global signals and power distribution across the chip.

Resistance and Capacitance Challenges

As interconnect dimensions shrink, both resistance and capacitance per unit length increase, creating the so-called "interconnect crisis." Resistance rises because wire cross-sectional area decreases while the electron mean free path becomes comparable to wire dimensions. Capacitance increases as wires crowd closer together.

The product of resistance and capacitance (RC) determines interconnect delay. Unlike transistor switching speed, which generally improves with scaling, interconnect delay can increase at smaller nodes. This reversal makes interconnect-aware design increasingly critical for high-performance circuits.

Several approaches address these challenges:

• Low-k dielectrics: Materials with lower dielectric constant reduce capacitance between adjacent wires
• Air gaps: Replacing dielectric with air in some regions minimizes capacitance
• Novel conductors: Ruthenium, cobalt, and other metals show promise for the narrowest wires
• Optimized via structures: Better vertical connections between metal layers reduce resistance
• Repeater insertion: Breaking long wires into shorter segments with buffers reduces delay

Power Distribution

Delivering clean power to billions of transistors across a chip becomes increasingly challenging at each node. The resistance of power distribution networks causes IR drop, reducing the voltage available at transistors far from power pins. This voltage variation affects timing and functionality.

Power distribution typically uses a grid structure with thick upper metal layers carrying current from package connections and progressively finer grids distributing power locally. Decoupling capacitors, either discrete components on the package or integrated on the die, help maintain stable voltage during current transients.

Advanced techniques for power distribution include:

• Backside power delivery: Routing power from the back of the die separates power and signal routing
• Through-silicon vias: Vertical connections through the silicon reduce distribution resistance
• Adaptive voltage scaling: Adjusting voltage based on operating conditions optimizes power and performance

Types of Design Rules

Design rules fall into several categories:

Width rules: Specify minimum widths for features such as metal lines, polysilicon gates, and diffusion regions. Features narrower than the minimum may not print reliably or may suffer excessive resistance.

Spacing rules: Define minimum separations between features on the same layer. Inadequate spacing can cause short circuits or yield problems. Different rules may apply depending on the feature types involved.

Enclosure rules: Specify how much one layer must surround another. For example, how much a contact must be enclosed by the metal above and below it. These rules ensure reliable connections despite alignment variations.

Extension rules: Define how far features must extend beyond other features. A gate must extend past the active region by a minimum amount to ensure the transistor functions correctly.

Area rules: Specify minimum sizes for certain features, often related to lithography or etch limitations. Very small features may not print or may etch away unpredictably.

Rule Complexity at Advanced Nodes

Design rule complexity has exploded at advanced nodes. Where older processes might have hundreds of rules, modern processes have tens of thousands. This complexity arises from several factors:

Multi-patterning: When the minimum pitch exceeds the resolution of a single lithography exposure, features must be split across multiple masks. Strict rules govern which features can share a mask and how split features interact.

Tip-to-tip rules: The spacing between the ends of adjacent lines often requires more distance than side-to-side spacing. Complex rules capture these directional dependencies.

Context-dependent rules: The required spacing between two features may depend on nearby features, local pattern density, or other contextual factors. These conditional rules capture complex lithography and process effects.

Recommended rules: Beyond mandatory rules, foundries provide recommendations for improved yield or reliability. Following these suggestions may improve manufacturability but is not strictly required.

Design Rule Checking

Electronic Design Automation (EDA) tools automatically verify that layouts satisfy design rules. Design Rule Checking (DRC) runs through the layout, comparing all features against the applicable rules and flagging violations.

Modern DRC involves sophisticated pattern matching and geometric analysis. Rule decks, provided by foundries, encode the thousands of checks required for advanced processes. Running a complete DRC on a large chip can take hours or days of computation.

Designers typically run DRC iteratively during layout, fixing violations as they arise. Final signoff DRC before tapeout must complete with zero violations, as even a single violated rule can cause chip failure.

Performance Metrics

Key performance parameters characterize process capabilities:

Transistor speed: Often characterized by frequency metrics like fT (transition frequency) or fmax (maximum oscillation frequency), or by ring oscillator frequency. Faster transistors enable higher clock frequencies and faster switching in digital logic.

Drive current: The current a transistor can deliver, typically specified as Ion at given conditions. Higher drive current enables faster charging of load capacitance.

Leakage current: The current flowing when a transistor should be off. Lower leakage enables better power efficiency, particularly important for mobile and battery-powered applications.

Switching energy: The energy consumed per transistor switching event. Lower switching energy enables better power efficiency in active operation.

Foundries typically offer multiple transistor variants within a node, optimizing different metrics. High-performance variants emphasize speed at the cost of leakage. Low-power variants minimize leakage at some speed penalty. Standard variants balance these characteristics.

Voltage Considerations

Supply voltage has decreased with scaling, from 5V in older technologies to around 0.7-0.8V at the most advanced nodes. Lower voltage reduces power consumption quadratically (since power scales with voltage squared) but also reduces noise margins and available signal swing.

Threshold voltage, the gate voltage at which a transistor begins conducting, must scale roughly with supply voltage to maintain performance. However, lowering threshold voltage exponentially increases leakage current. This tension between performance and leakage becomes increasingly severe at advanced nodes.

Many designs use multiple voltage domains, with higher voltages for I/O interfaces and lower voltages for core logic. Level shifters convert signals between domains. Careful power management minimizes total power while maintaining required performance.

Analog and Mixed-Signal Considerations

While digital scaling has driven most process development, analog and mixed-signal circuits face different challenges. Lower supply voltages reduce available signal headroom. Increased transistor variability degrades matching, critical for precision analog circuits. Smaller transistors exhibit more noise.

Advanced nodes often provide optional features supporting analog design:

• Thick-oxide devices: Higher-voltage transistors for analog and I/O functions
• Precision resistors: Accurate resistance values for analog circuits
• High-density capacitors: Metal-insulator-metal (MIM) or metal-oxide-metal (MOM) structures
• Isolated transistors: Deep n-well or triple-well structures for noise isolation

Some applications use older process nodes for analog functions, integrating with advanced digital processes through chiplet or package-level integration.

Wafer Cost

The cost to process a single wafer through a fabrication facility increases substantially at each node. More process steps, more expensive equipment, tighter controls, and lower yields all contribute. A wafer processed at the 3 nm node costs several times more than at 28 nm.

Key cost drivers include:

• Lithography: EUV (Extreme Ultraviolet) lithography tools cost over $100 million each and require multiple exposures for some layers
• Mask costs: A complete mask set for an advanced node can cost $10-20 million or more
• Process complexity: More than 1000 process steps for leading-edge nodes
• Metrology and inspection: Advanced measurement and defect detection throughout the process
• Yield learning: Significant investment in ramping yield to profitable levels

Design Costs

The cost of designing a chip has increased even faster than manufacturing costs. More complex design rules, verification challenges, and longer development cycles all contribute. Designing a complex chip at an advanced node can cost hundreds of millions of dollars.

Major design cost components include:

Engineering labor: Large teams work for years on advanced designs. Scarce expertise commands premium compensation.

EDA tools: Licenses for sophisticated design tools represent significant ongoing expense.

IP licensing: Third-party IP blocks for standard functions reduce design effort but add licensing costs.

Verification: Ensuring correct functionality requires extensive simulation, emulation, and formal verification. Verification often consumes more effort than design.

Physical design: Place and route, timing closure, and physical verification become increasingly challenging and time-consuming.

Economics of Volume

High fixed costs and relatively lower marginal costs create strong economies of scale. Once a design is complete and manufacturing is qualified, each additional chip costs relatively little to produce. This favors high-volume products that can amortize development costs across millions or billions of units.

The break-even volume for advanced nodes has increased substantially. Where a 180 nm design might break even at tens of thousands of units, a leading-edge design may require millions. This reality has driven many applications to remain at older, more economical nodes.

Foundry business models have evolved to address cost challenges:

• Multi-project wafers: Sharing mask and wafer costs among multiple designs reduces prototyping expense
• Shuttle services: Scheduled manufacturing runs aggregate small orders for cost efficiency
• IP reuse: Verified IP blocks spread development costs across multiple products
• Platform designs: Customizable base designs reduce per-product engineering

Historical Roadmapping

The Semiconductor Industry Association (SIA) began publishing technology roadmaps in the 1990s, which evolved into the International Technology Roadmap for Semiconductors (ITRS). These documents projected feature sizes, performance targets, and material requirements for upcoming generations.

The ITRS served multiple purposes:

• Coordination: Aligning equipment, materials, and design tool development with manufacturing roadmaps
• Investment guidance: Helping companies plan capital investments and R&D priorities
• Challenge identification: Highlighting technical barriers requiring innovation
• Standardization: Promoting compatible interfaces and specifications

For decades, the industry roughly followed roadmap projections, with feature sizes halving approximately every two years as predicted by Moore's Law. This predictability enabled long-term planning across the semiconductor ecosystem.

Modern Roadmapping Challenges

The ITRS concluded in 2016, replaced by the International Roadmap for Devices and Systems (IRDS). This transition reflected fundamental changes in industry dynamics. Pure geometric scaling had become economically limited, and multiple paths forward existed rather than a single clear trajectory.

Current roadmapping faces several challenges:

Divergent approaches: Different companies pursue different transistor architectures, integration schemes, and packaging technologies. No single roadmap captures all viable paths.

Economic factors: What is technically possible may not be economically feasible. Cost-performance tradeoffs increasingly influence technology choices.

Application diversity: Different markets (mobile, data center, automotive, IoT) have different requirements, leading to specialized solutions rather than one-size-fits-all scaling.

Proprietary development: Leading companies guard competitive technology plans, limiting shared roadmapping.

Future Directions

Several technology directions feature in current roadmaps and projections:

Continued transistor scaling: Gate-all-around transistors, complementary FETs (CFETs), and other innovations extend transistor scaling, though at increasing cost and complexity.

Advanced packaging: 3D stacking, chiplets, and heterogeneous integration provide scaling benefits through integration rather than transistor shrinking.

New materials: High-mobility channel materials, novel dielectrics, and improved conductors may enable continued performance improvement.

Beyond-CMOS technologies: Spintronic, neuromorphic, and quantum approaches may complement or eventually supersede conventional transistors.

Design-technology co-optimization: Jointly optimizing circuit design and process technology extracts maximum benefit from available capabilities.

The semiconductor industry continues to innovate, though the path forward is less clearly defined than in previous decades. Multiple technologies and approaches coexist, with different solutions optimal for different applications.

Performance Requirements

High-performance computing, graphics processors, and other demanding applications often justify advanced nodes despite their cost. The performance advantages of smaller, faster transistors can be essential for competitive products.

However, not all performance comes from transistor scaling. Architecture improvements, algorithm optimization, and system-level design can achieve significant gains independent of process technology. Evaluating whether an application truly requires leading-edge transistors helps avoid unnecessary cost and complexity.

Power and Energy Efficiency

Mobile devices and battery-powered applications prioritize power efficiency. Advanced nodes can offer better energy per operation through lower supply voltage and smaller capacitance. However, increased leakage at advanced nodes can offset these gains for lightly loaded circuits.

Workload characteristics matter: applications with high activity factors benefit most from advanced nodes, while standby-dominated applications may prefer older nodes with lower leakage. Careful analysis of the actual use case guides optimal node selection.

Cost Optimization

For cost-sensitive applications, older nodes often provide better economics. A design that meets requirements at 28 nm costs far less to develop and manufacture than the same function at 7 nm. Many industrial, automotive, and consumer applications successfully use mature nodes.

Total cost analysis should include:

• Development cost: Design effort, tools, and IP at different nodes
• Mask and NRE costs: One-time manufacturing preparation expenses
• Per-unit manufacturing cost: Wafer cost divided by good die per wafer
• Volume projections: How many units will amortize fixed costs
• Product lifetime: How long the product will be manufactured and sold

Schedule and Risk

Newer nodes carry more technical risk and typically require longer development cycles. Design rules are less mature, fewer IP blocks are available, and yield learning continues during early production. Projects with aggressive schedules or low risk tolerance may benefit from more established nodes.

Foundry capacity and allocation also matter. Leading-edge capacity is scarce and commands premium pricing. Mature nodes offer more capacity, more foundry options, and often better supply security.