Electronics Guide

Why Sequencing Matters

The most common concern in power sequencing is latch-up, a potentially destructive condition that can occur in CMOS devices. Every CMOS transistor contains parasitic bipolar structures that form a thyristor-like path between the power supply and ground. If certain voltage conditions occur during power-up, these parasitic structures can turn on and create a low-impedance path that draws excessive current. This condition is self-sustaining once triggered and can cause permanent damage through localized heating.

Beyond latch-up prevention, proper sequencing ensures that I/O pins do not experience voltages outside their rated ranges relative to their power supplies. When an I/O buffer's supply is unpowered while its associated core logic is active, the ESD protection structures on the I/O pins may become forward-biased, potentially damaging the pin or allowing current to flow into unintended paths. Similar issues arise when interfacing between devices that power up at different times.

Sequencing also addresses initialization requirements. Many digital devices require specific power supply conditions before they can properly configure their internal state machines, phase-locked loops, and other initialization-sensitive circuits. Improper sequencing may result in devices that appear to power up but fail to initialize correctly, leading to subtle and hard-to-diagnose system failures.

Common Sequencing Requirements

Device manufacturers specify sequencing requirements in their datasheets, typically using one of several common patterns. The most straightforward requirement is sequential ordering, where rails must power up in a specific sequence with Rail A reaching its target voltage before Rail B begins ramping. This is common for devices where the core supply must be established before I/O supplies.

Ratiometric sequencing requires voltage rails to maintain a specific relationship during the ramp, such as Rail B always being less than or equal to Rail A plus some offset. This approach is useful when the relationship between voltages matters more than absolute timing.

Simultaneous sequencing requires multiple rails to ramp together, reaching their target voltages at approximately the same time. This can be more challenging to implement but simplifies the requirements for devices sensitive to inter-rail voltage differences.

Many modern devices combine these requirements, specifying sequential ordering for some rail pairs while requiring ratiometric tracking for others. Complex devices may have sequencing requirements that span multiple pages of the datasheet.

Fixed Sequence Controllers

The simplest sequencing solutions use fixed-function controllers with predetermined sequencing behavior. These devices typically provide a specific number of enable outputs that activate in a fixed order, with timing controlled by external RC networks or internal delay generators. Fixed sequence controllers are cost-effective and easy to use when their built-in sequence matches the application requirements.

Many integrated power management ICs include fixed sequencing for their internal regulators. These PMICs are designed for specific processor families and implement the required sequencing automatically, simplifying the design process for common applications.

Programmable Sequencers

Programmable power sequencers offer greater flexibility, allowing designers to define custom sequences through pin-strapping, register configuration, or external EEPROM storage. These devices can implement arbitrary sequencing relationships, complex timing requirements, and sophisticated fault handling strategies.

Pin-strapped configuration uses external resistor networks to set sequencing parameters. This approach offers moderate flexibility without requiring programming tools, making it suitable for moderate-volume production where different product variants may require different sequences.

Register-based and EEPROM-based programmable sequencers provide the most flexibility, supporting complex sequences with conditional logic, multiple timing phases, and sophisticated fault response configurations. These devices are typically configured during manufacturing using I2C, PMBus, or proprietary programming interfaces.

Timing Configuration

Sequence timing is typically defined through delay parameters that specify the time between events. Common timing parameters include the delay from one rail reaching its target to the next rail beginning its ramp, the minimum time a rail must remain stable before dependent rails can start, and the maximum time allowed for a rail to reach its target voltage.

Timing accuracy requirements vary by application. Some devices tolerate relatively loose timing with delays accurate to within 10-20 percent, while others require microsecond-level precision. The sequencing controller's timing accuracy must match the most stringent requirement in the system.

Threshold Detection

Voltage monitoring typically involves comparing each supply against one or more threshold levels. The most common thresholds include power-good thresholds that indicate when a supply has reached an acceptable operating voltage, undervoltage thresholds that detect when a supply has dropped below safe limits, and overvoltage thresholds that detect potentially damaging high-voltage conditions.

These thresholds are usually set as percentages of the nominal supply voltage, with typical values of 90-95 percent for power-good, 85-90 percent for undervoltage warning, and 110-115 percent for overvoltage detection. Some controllers allow independent configuration of rising and falling thresholds to implement hysteresis and prevent oscillation near threshold boundaries.

Monitoring Architectures

Sequencing controllers use various architectures for voltage monitoring. Dedicated comparator inputs provide the fastest response and most accurate threshold detection, with each monitored supply having its own comparison circuit. This approach is common in high-reliability applications where rapid fault detection is critical.

Multiplexed ADC monitoring uses a single analog-to-digital converter that sequentially samples multiple supply voltages. This approach is more economical for monitoring many supplies but introduces sampling latency that may be unsuitable for detecting fast transients. The sampling rate must be fast enough to detect supply deviations before they can cause damage.

Some controllers combine both approaches, using dedicated comparators for critical thresholds like overvoltage detection while using multiplexed ADC monitoring for less time-critical functions like temperature logging and efficiency calculations.

Glitch Filtering

Real power supplies exhibit transient behavior during load changes, and monitoring systems must distinguish between brief transients and genuine fault conditions. Glitch filtering, also called deglitching or blanking, requires a threshold violation to persist for a minimum time before triggering a fault response.

Filter times are typically configurable, ranging from microseconds for fast fault detection to milliseconds for applications where transient excursions are expected and acceptable. The filter time must be short enough to detect genuine faults before damage occurs while being long enough to avoid false triggers from normal operating transients.

Inrush Current Management

Without soft-start control, a voltage regulator attempts to charge its output capacitance as quickly as possible when enabled. The charging current is limited only by the regulator's current capability and output impedance, potentially causing large current spikes that stress input supplies, create voltage droops on shared power rails, and generate electromagnetic interference.

Soft-start limits the output voltage ramp rate, which in turn limits the current required to charge output capacitors. The relationship between ramp rate, capacitance, and current follows from the basic capacitor equation: the current equals capacitance multiplied by the rate of voltage change. Slower ramps require less current, reducing stress throughout the power system.

Soft-Start Implementation

Internal soft-start is built into most modern voltage regulators and typically uses a capacitor charged by an internal current source to generate a ramping reference voltage. The regulator's output tracks this reference during startup, ensuring a controlled ramp regardless of load conditions. The soft-start time is usually set by an external capacitor connected to a dedicated pin.

External soft-start control from a sequencing controller provides more flexibility and coordination between multiple supplies. The controller generates ramping enable signals or reference voltages that control when and how fast each supply reaches its target. This approach allows the sequencing controller to implement coordinated ramps for ratiometric tracking or simultaneous sequencing.

Some sequencers provide programmable voltage references that ramp at controlled rates, allowing precise control of output voltage trajectories. These references can implement linear ramps, stepped ramps, or more complex profiles as required by specific applications.

Pre-Bias Protection

Pre-bias refers to the condition where a power supply's output has residual voltage from a previous power cycle or from back-feeding through load connections. When a supply with soft-start attempts to start into a pre-biased output, problems can occur if the regulator tries to pull its output down to match the soft-start reference.

Pre-bias safe soft-start implementations detect existing output voltage and begin the soft-start ramp from that level rather than from zero. This prevents current from flowing backward through the regulator's output stage and avoids voltage reversals that could stress the load. Most modern switching regulators include pre-bias safe operation, but designers must verify this capability when selecting components for systems where pre-bias conditions may occur.

Signal Characteristics

Power-good outputs are typically open-drain or open-collector, allowing multiple signals to be wire-ANDed together for combined status indication. When active, the power-good signal indicates that monitored supplies are within their specified voltage ranges and have been stable for any required settling time. When inactive, the signal indicates that one or more monitored conditions have failed.

The timing relationship between supply voltage reaching its target and power-good assertion is critical. Most systems require a delay between voltage reaching specification and power-good assertion to ensure supplies have fully settled and output capacitors are charged. This delay, typically ranging from hundreds of microseconds to several milliseconds, prevents dependent circuits from attempting operation before power is truly stable.

Cascaded Power-Good

In systems with multiple sequencing stages, power-good signals often cascade from one stage to the next. Each stage waits for the previous stage's power-good before beginning its sequence. This creates a chain of dependencies that naturally implements complex sequencing without requiring a central controller to manage all timing relationships.

Cascaded power-good architectures offer modularity benefits, allowing subsystems to be designed and tested independently. Each subsystem manages its internal sequencing and presents a single power-good output indicating when it is ready for dependent systems to proceed. This approach scales well to complex systems with many voltage rails.

Power-Good as Reset Control

Power-good signals commonly connect to processor reset inputs, either directly or through reset generation circuits. This connection ensures that processors and other digital logic remain in reset until all required supplies are stable, preventing undefined behavior during power transitions.

The power-good to reset relationship must account for any additional initialization requirements beyond power supply stability. Some systems require external clock signals to be stable, configuration data to be available, or other conditions to be met before reset can be released. Reset generators often combine multiple input conditions, releasing reset only when all prerequisites are satisfied.

Fault Detection

Common fault conditions include undervoltage, where a supply drops below acceptable limits due to overload, regulation failure, or input power loss; overvoltage, where a supply exceeds safe limits due to regulation failure or transient conditions; overcurrent, where excessive load current indicates a short circuit or component failure; and overtemperature, where thermal limits are exceeded due to inadequate cooling or excessive power dissipation.

Fault detection typically combines threshold comparison with time filtering to distinguish genuine faults from transient excursions. Critical faults like overvoltage may require immediate response without filtering, while less critical conditions may allow longer filter times to prevent nuisance trips during normal operating transients.

Fault Response Strategies

When a fault is detected, the sequencing controller must execute an appropriate response. Common response options include immediate shutdown, where all supplies are disabled as quickly as possible to prevent damage; sequential shutdown, where supplies are disabled in reverse sequence order to maintain proper voltage relationships during power-down; fault isolation, where only the faulted supply and its dependents are disabled while other system sections continue operation; and retry, where the system attempts to restart after a fault, useful for handling transient conditions that may clear themselves.

The appropriate response depends on the fault type and system requirements. Overvoltage faults typically require immediate shutdown due to the potential for rapid damage. Undervoltage faults may allow more graceful sequential shutdown if the condition develops gradually. Current-limited faults in non-critical supplies might be handled through isolation to maintain partial system operation.

Fault Logging and Reporting

Advanced sequencing controllers include fault logging capabilities that record fault conditions, timing, and sequences of events leading to shutdown. This information is invaluable for debugging power-related failures, which can otherwise be difficult to diagnose because the evidence is lost when power is removed.

Fault information may be stored in non-volatile memory for retrieval after power is restored, transmitted over a management interface during or immediately after the fault, or indicated through status LEDs or other physical indicators. Systems with high availability requirements often include dedicated management controllers that can access fault information even when the main system is not operational.

Reset Signal Generation

Reset signals must meet specific timing and electrical requirements defined by the devices they control. Processors typically specify minimum reset pulse widths, setup times relative to clock signals, and voltage level requirements. Reset generation circuits must satisfy these requirements while coordinating with power supply status and other system conditions.

Active-low reset is the most common convention, with the reset signal held low during power-up and transitioning high when the system is ready for operation. Some devices use active-high reset, requiring inverted logic. Reset generation circuits must account for the specific requirements of all devices in the system.

Reset Timing Considerations

The timing of reset release relative to power supply stability is critical for reliable operation. Reset should remain asserted until all supplies required by the device have reached their specified voltages and stabilized. Additional hold time after supplies stabilize allows for settling of internal device circuits before operation begins.

Clock stability is another common reset prerequisite. Many processors require their clock inputs to be stable and running at the correct frequency before reset is released. Reset generation may need to monitor clock presence or include delays that account for clock oscillator startup times.

Watchdog Integration

Watchdog timers provide ongoing monitoring of system operation and can trigger reset if the system fails to service the watchdog within specified time limits. Integrating watchdog functionality with power sequencing ensures that watchdog-triggered resets execute properly coordinated power cycling rather than simply toggling the reset signal.

When a watchdog timeout occurs, the system may need to execute a full power-down and power-up sequence rather than a simple reset to clear fault conditions that a reset alone cannot resolve. The sequencing controller can coordinate this full power cycle while maintaining proper sequencing throughout the process.

Component Selection

Selecting an appropriate sequencing controller requires matching the controller's capabilities to the application requirements. Key parameters include the number of monitored and controlled channels, timing accuracy and range, fault detection capabilities, programming flexibility, and communication interfaces for configuration and monitoring.

Voltage regulators must be compatible with the sequencing approach, supporting enable control, soft-start adjustment, and proper behavior under all sequencing scenarios including pre-biased startup. Regulators with integrated sequencing features may simplify designs when their built-in capabilities match the requirements.

System Architecture

The sequencing architecture should balance complexity against reliability and maintainability. Centralized architectures using a single sequencing controller offer coordinated control and unified fault handling but create a single point of failure. Distributed architectures with cascaded power-good signals provide better modularity and fault isolation but may be more complex to debug.

Sequencing timing budgets must account for worst-case component tolerances, temperature variations, and aging effects. Designs should include appropriate margins to ensure reliable operation throughout the product lifetime under all specified conditions.

Validation and Testing

Power sequencing validation requires testing under a range of conditions including nominal operation, voltage and temperature extremes, and various fault injection scenarios. Automated test equipment can verify timing relationships and fault responses that would be difficult to validate manually.

Production testing should verify correct sequencing configuration and operation. This may include functional tests that verify power-up sequences and fault responses, as well as parametric tests that verify timing and threshold accuracy. Test coverage must be sufficient to detect configuration errors and component defects that could cause field failures.