Electronics Guide

Architectural State

The ISA defines the architectural state that is visible to programs and must be preserved across context switches:

• General-purpose registers: A set of fast storage locations for holding operands and intermediate results, typically 8 to 32 registers in modern architectures
• Program counter: The address of the next instruction to execute, updated by sequential execution or branch instructions
• Status flags: Condition codes reflecting the results of previous operations, such as zero, negative, carry, and overflow flags
• Memory: The addressable storage space accessible through load and store operations
• Special registers: Control registers, stack pointers, and other architecture-specific registers

This defined state ensures that software behaves consistently regardless of how the hardware implements instruction execution internally.

Software Compatibility

A well-designed ISA provides long-term software compatibility. Programs compiled for an ISA continue to run on newer processor implementations, protecting software investments across hardware generations. This backward compatibility is a defining characteristic of successful instruction sets like x86, which has maintained compatibility with software written decades ago while continuously evolving.

The ISA specification must be precise enough to ensure consistent behavior across implementations but abstract enough to permit diverse microarchitectural optimizations. This balance between specificity and flexibility is a fundamental challenge in architecture design.

CISC Architecture Principles

Complex Instruction Set Computer architectures emerged when memory was expensive and slow relative to processor logic. CISC designs aimed to maximize the work done per instruction, reducing program size and memory bandwidth requirements:

• Rich instruction set: Hundreds of instructions covering specialized operations, reducing the number of instructions needed for common tasks
• Variable-length instructions: Encodings from one byte to fifteen or more bytes, providing compact code for frequent operations
• Memory-to-memory operations: Instructions that read operands from memory, perform computations, and write results back to memory in a single instruction
• Complex addressing modes: Sophisticated memory addressing calculations performed by hardware, including indexed, indirect, and auto-increment modes
• Microcode implementation: Complex instructions implemented as sequences of simpler micro-operations, allowing sophisticated behavior without proportionally complex control logic

The x86 architecture exemplifies CISC design, with instructions that can perform string operations, memory-to-memory moves, and complex address calculations. This richness allows compact, expressive assembly code but creates challenges for high-performance implementation.

RISC Architecture Principles

Reduced Instruction Set Computer architectures emerged in the 1980s based on the observation that compilers rarely used complex CISC instructions. RISC designs optimize for the common case, enabling simpler and faster implementations:

• Load-store architecture: Only load and store instructions access memory; all computations operate on registers
• Fixed-length instructions: Uniform instruction size (typically 32 bits) simplifies instruction fetch and decode
• Simple addressing modes: Limited to register plus offset addressing, simplifying address calculation
• Large register files: More registers reduce memory traffic and provide compiler optimization opportunities
• Hardwired control: Simple instructions execute in single cycles without microcode overhead
• Optimizing compilers: Reliance on sophisticated compilers to generate efficient code sequences

ARM, MIPS, and RISC-V exemplify this philosophy, with regular instruction formats that enable efficient pipelining and simplified decoder design.

Modern Convergence

Contemporary processors have largely converged toward hybrid approaches that combine the best aspects of both philosophies:

• CISC front-end, RISC back-end: Modern x86 processors decode complex instructions into simpler micro-operations that execute on RISC-like execution units
• Instruction fusion: RISC processors combine common instruction pairs into single operations for improved efficiency
• Macro-operation fusion: Detecting patterns like compare-and-branch to execute as unified operations
• Extended instruction sets: RISC architectures adding specialized complex instructions for cryptography, vector processing, and other domains

The distinction between RISC and CISC has become less meaningful for programmers, as both styles achieve high performance through sophisticated microarchitectures. The ISA visible to software matters less than the underlying implementation efficiency.

Fixed-Length Formats

Fixed-length instruction encoding uses the same number of bits for every instruction, typically 32 bits in modern RISC architectures. This uniformity offers significant advantages:

• Simplified fetch: Each fetch retrieves exactly one instruction, and instruction boundaries are always known
• Parallel decode: Multiple instructions can be decoded simultaneously without first determining instruction lengths
• Branch target simplicity: Branch offsets are always at the same position within the instruction word
• Predictable memory access: Instruction cache and prefetch behavior are regular and predictable

The limitation is code density: simple operations that could be encoded in fewer bits still consume the full instruction width. RISC-V addresses this with an optional compressed instruction extension that adds 16-bit encodings for common operations.

Variable-Length Formats

Variable-length encoding uses different numbers of bytes for different instructions. x86, for example, uses instructions ranging from one to fifteen bytes:

• Code density: Common operations use compact encodings, while rare complex operations can specify more operands
• Addressing flexibility: Different addressing modes can be encoded with varying amounts of specifier data
• Backward compatibility: New instructions can be added using previously unused prefixes and escape codes

Variable length creates decode complexity. The processor must examine each byte sequentially to determine where instructions begin and end. Modern x86 processors include sophisticated predecode hardware and instruction boundary markers in the instruction cache to manage this complexity.

Common Format Types

Within an ISA, instructions typically follow several standard formats based on the number and type of operands:

• R-type (Register): Three register operands for arithmetic operations (e.g., ADD R1, R2, R3)
• I-type (Immediate): Two registers plus an immediate constant (e.g., ADDI R1, R2, 100)
• S-type (Store): Two registers plus offset for store operations
• B-type (Branch): Two registers plus branch offset for conditional branches
• J-type (Jump): Large immediate field for jump targets
• U-type (Upper immediate): Large immediate for loading upper bits of constants

Each format allocates the instruction bits differently to accommodate its specific needs while maintaining regular field positions where possible to simplify decoding.

Register Addressing

The operand is contained in a processor register, specified by a register number in the instruction. Register addressing is the fastest access method since no memory access is required. Most arithmetic and logical operations use register operands exclusively in load-store architectures.

Example: ADD R3, R1, R2 adds the contents of R1 and R2, storing the result in R3.

Immediate Addressing

The operand value is encoded directly within the instruction. Immediate addressing provides constants without requiring a prior load from memory. The immediate field size limits the range of representable values:

• Sign extension: Small immediates are typically sign-extended to the full register width
• Split immediates: Some architectures split immediate fields across non-contiguous bits to maintain regular encoding
• Shifted immediates: ARM allows rotation of immediates to represent a wider range of useful values

Example: ADDI R2, R1, 42 adds the immediate value 42 to R1, storing the result in R2.

Base Plus Offset Addressing

A memory address is computed by adding a signed offset (typically immediate) to a base register. This fundamental addressing mode supports:

• Local variable access: Offset from frame pointer or stack pointer
• Structure field access: Base points to structure, offset selects field
• Array access: Base points to array start, offset computed from index

Example: LW R1, 16(R2) loads a word from the address computed as R2 + 16.

Indexed Addressing

The effective address is the sum of two registers, useful for array access when the index is computed at runtime:

Example: LW R1, (R2 + R3) loads from the address computed as R2 plus R3. Some architectures allow scaling the index register to match element size.

PC-Relative Addressing

The address is computed relative to the program counter, essential for position-independent code:

• Branches: Target address specified as offset from current instruction
• Literal pools: Constants stored near the code and accessed via PC-relative loads
• Global data: Position-independent access to global variables

PC-relative addressing enables code that executes correctly regardless of where it is loaded in memory, crucial for shared libraries and relocatable code.

Complex Addressing Modes

CISC architectures support more elaborate addressing calculations:

• Indirect: A register contains the address of the actual operand address
• Auto-increment/decrement: The base register is automatically updated after use, useful for traversing arrays and stack operations
• Scaled indexed: Index multiplied by element size (base + index * scale + offset)
• Memory indirect: Address read from memory points to actual operand

These modes reduce instruction count but increase hardware complexity. Modern CISC implementations often decompose complex addressing into simpler micro-operations internally.

Integer Data Types

Processors typically support multiple integer sizes to balance precision against memory and bandwidth requirements:

• Byte (8 bits): Characters, small counters, packed data
• Halfword (16 bits): Unicode characters, audio samples, short integers
• Word (32 bits): Standard integers, pointers in 32-bit architectures
• Doubleword (64 bits): Long integers, pointers in 64-bit architectures
• Quadword (128 bits): Extended precision, SIMD operations

Both signed (two's complement) and unsigned interpretations are typically supported, with different instructions or flags controlling the interpretation for comparisons and arithmetic.

Floating-Point Types

Floating-point support follows IEEE 754 standard formats:

• Single precision (32 bits): Approximately 7 decimal digits of precision, sufficient for graphics and many scientific applications
• Double precision (64 bits): Approximately 16 decimal digits, the default for most scientific computing
• Extended precision (80 bits): Used internally by x87 FPU for intermediate results
• Half precision (16 bits): Increasingly important for machine learning inference

Floating-point operations often execute in separate register files and execution units, with the ISA defining rounding modes, exception behavior, and special value handling.

Memory Alignment

Many architectures require or recommend that data be aligned to addresses that are multiples of the data size:

• Strict alignment: Unaligned accesses cause exceptions (older RISC architectures)
• Performance penalty: Unaligned accesses work but execute slower (most modern architectures)
• Full support: Hardware handles unaligned accesses with minimal or no penalty (x86)

Alignment considerations affect structure layout, array packing, and memory allocation. Compilers typically insert padding to maintain alignment.

Endianness

Endianness determines the byte ordering within multi-byte data types:

• Big-endian: Most significant byte at lowest address (network byte order, older Motorola, IBM)
• Little-endian: Least significant byte at lowest address (x86, most ARM configurations)
• Bi-endian: Configurable endianness (ARM, MIPS, PowerPC)

Endianness affects data interchange between systems and the interpretation of memory dumps. Network protocols typically use big-endian format, requiring conversion on little-endian systems.

Opcode Assignment

The opcode field identifies the operation to perform. Encoding strategies include:

• Fixed opcode position: Opcode always in the same bit positions, simplifying initial decode
• Hierarchical encoding: Main opcode field plus secondary fields for instruction variants
• Huffman-like encoding: Frequent operations get shorter encodings (variable-length ISAs)
• Escape codes: Special opcode values signal that additional bytes specify the operation

Modern RISC architectures typically use fixed opcode positions with additional function fields to distinguish instruction variants within a category.

Register Encoding

Register specifiers identify which registers to use. With N registers, each specifier requires log2(N) bits:

• 8 registers: 3 bits per specifier (original x86)
• 16 registers: 4 bits per specifier (x86-64, AArch64)
• 32 registers: 5 bits per specifier (RISC-V, MIPS, ARM)

Three-operand formats require 9-15 bits just for register specification, constraining the immediate field size in fixed-width instructions.

Immediate Encoding

Immediate fields encode constant values within instructions. Various techniques extend the range of representable immediates:

• Sign extension: Small immediates sign-extended to full width for negative values
• PC-relative encoding: Branch offsets multiplied by instruction size to extend range
• Upper immediate instructions: Separate instruction to load upper bits, combined with lower immediate
• Rotated immediates: ARM allows 8-bit values rotated by multiples of 2, representing many useful constants
• Move-wide immediate: Place a 16-bit immediate at any position within a 64-bit register

Loading arbitrary 32-bit or 64-bit constants typically requires multiple instructions or loading from a literal pool in memory.

Prefix and Suffix Bytes

Variable-length architectures use prefix and suffix bytes to modify instruction behavior:

• REX prefix (x86-64): Enables access to extended registers and 64-bit operand sizes
• VEX/EVEX prefixes: Enable AVX vector instructions with additional register specifiers
• Lock prefix: Makes memory operations atomic for multiprocessor synchronization
• Segment overrides: Select non-default memory segment (legacy use)

Prefixes add flexibility but increase decoder complexity and can affect instruction timing.

Condition Codes

Many architectures maintain status flags that reflect the result of the previous operation:

• Zero (Z): Set when the result is zero
• Negative/Sign (N): Set when the result is negative (most significant bit is 1)
• Carry (C): Set when unsigned arithmetic produces a carry out
• Overflow (V): Set when signed arithmetic produces overflow

Conditional branches test combinations of these flags to implement all comparison operations. For example, testing for signed less-than checks if N differs from V (N XOR V = 1).

Conditional Branch Instructions

Conditional branches transfer control based on flag values:

• Compare-then-branch: Separate comparison instruction sets flags, followed by conditional branch
• Combined compare-and-branch: Single instruction compares operands and branches
• Branch conditions: Equal, not equal, less than (signed/unsigned), greater than, and combinations

Branch prediction attempts to guess the branch outcome before it is known, allowing speculative execution. Mispredictions incur significant penalties as the pipeline must be flushed.

Predicated Instructions

Some architectures allow any instruction to be conditionally executed based on flags, eliminating branches entirely:

• Full predication: Every instruction includes a condition field (ARM32, IA-64)
• Conditional moves: Move instructions that only update the destination if the condition is true (x86 CMOV, ARM CSEL)
• Select instructions: Choose between two sources based on condition

Predication converts control dependencies into data dependencies, potentially improving performance for short conditional sequences by avoiding branch misprediction penalties. However, predicated instructions always execute (consuming resources) even when their results are discarded.

Branchless Programming

Conditional moves enable branchless programming techniques that avoid unpredictable branches:

• Computing both paths: Calculate both outcomes, then select the correct one
• Bit manipulation: Use arithmetic and logical operations to produce conditional results
• Lookup tables: Index into a table rather than branching

Branchless techniques are valuable when branch prediction performs poorly, such as with random or data-dependent conditions. However, computing both paths wastes work when one path is much more expensive than the other.

SIMD Concepts

SIMD extends the processor's execution model to operate on vectors of data:

• Vector registers: Wide registers (128, 256, or 512 bits) holding multiple data elements
• Packed data types: A register might hold 16 bytes, 8 halfwords, 4 words, or 2 doublewords
• Parallel operations: A single instruction operates on all elements in parallel
• Element-wise semantics: Each lane operates independently, as if separate scalar operations

SIMD can provide 4x, 8x, or even 16x throughput improvement for suitable workloads, making it essential for high-performance computing.

x86 SIMD Evolution

Intel's SIMD extensions have evolved substantially:

• MMX (1997): 64-bit registers, integer operations, shared with x87 FPU registers
• SSE (1999): 128-bit XMM registers, single-precision floating-point
• SSE2 (2001): Double-precision floating-point, integer operations in XMM registers
• SSE3/SSSE3/SSE4: Horizontal operations, shuffle improvements, string processing
• AVX (2011): 256-bit YMM registers, three-operand syntax
• AVX2 (2013): 256-bit integer operations, gather instructions
• AVX-512 (2016): 512-bit ZMM registers, masking, embedded broadcast

Each generation added new capabilities while maintaining backward compatibility with previous extensions.

ARM SIMD

ARM processors provide SIMD through NEON and SVE extensions:

• NEON: 128-bit vectors with fixed length, widely deployed in mobile and embedded systems
• SVE (Scalable Vector Extension): Variable-length vectors from 128 to 2048 bits, allowing the same code to utilize different hardware implementations
• SVE2: Enhanced for general-purpose computing beyond high-performance computing

SVE's scalable approach allows code to automatically benefit from wider implementations without recompilation, simplifying software development and deployment.

SIMD Operations

Common SIMD instruction categories include:

• Arithmetic: Add, subtract, multiply, divide, min, max, absolute value
• Logical: AND, OR, XOR, NOT, shifts, rotates
• Comparison: Element-wise comparisons producing mask vectors
• Shuffle/permute: Rearranging elements within or across registers
• Pack/unpack: Converting between element sizes
• Horizontal operations: Operating across elements within a vector (sum, min, max)
• Memory operations: Aligned and unaligned loads/stores, gather/scatter

Masking and Predication

Modern SIMD extensions support per-element masking:

• Mask registers: Dedicated registers (k0-k7 in AVX-512) holding per-element mask bits
• Zeroing masking: Masked-out elements become zero
• Merging masking: Masked-out elements retain previous values
• Predicated SVE: All SVE operations accept predicate masks

Masking enables efficient handling of irregular data sizes, boundary conditions, and conditional operations within vectorized code.

Vector Registers and Length

Vector processors operate on very long vectors, potentially containing hundreds of elements:

• Vector length register: Specifies how many elements to process, enabling variable-length operation
• Maximum vector length: Hardware limit on elements per vector register
• Strip mining: Processing long arrays in chunks that fit the vector length

Unlike fixed-width SIMD, vector processors can efficiently handle any array length through vector length control.

Memory Access Patterns

Vector architectures provide sophisticated memory access instructions:

• Unit stride: Consecutive elements in memory, the most efficient pattern
• Strided access: Elements separated by a constant stride, common in matrix column access
• Indexed (gather/scatter): Elements at arbitrary addresses specified by an index vector
• Segmented access: Loading multiple vectors from interleaved data (e.g., RGB image data)

Efficient memory access is critical for vector performance, as memory bandwidth often limits achievable throughput.

Vector Chaining

Vector chaining allows the result of one vector operation to feed directly into the next without waiting for complete vector completion:

As soon as the first elements of a vector multiply complete, they can immediately enter the vector add unit. This pipelining of vector operations dramatically increases throughput compared to waiting for each operation to fully complete.

RISC-V Vector Extension

RISC-V's vector extension (RVV) provides a modern, clean vector architecture:

• Configurable vector length: Software queries hardware capability and sets desired configuration
• Type-agnostic registers: The same registers hold different element sizes based on configuration
• Mask registers: Per-element predication for conditional operations
• Reduction operations: Sum, min, max across vector elements

RVV's design allows efficient implementation across a wide range of hardware, from embedded microcontrollers to high-performance computing systems.

Cryptographic Extensions

Hardware acceleration for cryptographic operations provides both performance and security benefits:

• AES instructions: Single instructions for AES encryption rounds (x86 AES-NI, ARM AES)
• SHA instructions: Hardware acceleration for SHA-1 and SHA-256 hashing
• Polynomial multiplication: Carry-less multiplication for GCM mode and CRC
• Random number generation: Hardware random number generators accessible via instructions

Cryptographic instructions also resist timing-based side-channel attacks that can leak secrets in software implementations.

Machine Learning Extensions

The explosive growth of machine learning has driven new instruction set extensions:

• Intel AMX: Tile matrix multiplication for neural network inference and training
• ARM SME: Scalable Matrix Extension for matrix operations
• VNNI: Vector Neural Network Instructions for 8-bit and 16-bit integer dot products
• BF16: Brain Float 16 format optimized for machine learning

These extensions provide orders of magnitude performance improvement for neural network workloads compared to general-purpose instructions.

Atomic and Synchronization Extensions

Multiprocessor systems require atomic operations for thread synchronization:

• Compare-and-swap: Atomic read-modify-write for lock-free algorithms
• Load-linked/store-conditional: Alternative atomic primitive with lower overhead
• Fetch-and-add: Atomic increment for counters and reference counting
• Memory barriers: Ordering constraints for memory operations
• Transactional memory: Hardware support for atomic transaction regions

Efficient synchronization primitives are essential for scaling parallel applications across many processor cores.

Virtualization Extensions

Hardware support for virtualization improves hypervisor performance:

• Nested page tables: Hardware translation for guest physical addresses
• VM entry/exit acceleration: Fast world switches between host and guest
• Virtual interrupt handling: Direct delivery of interrupts to guests
• Device virtualization: Hardware assistance for I/O virtualization

Virtualization extensions enable running multiple operating systems on a single physical processor with minimal overhead.

Security Extensions

Hardware security features protect against software attacks:

• Memory tagging: ARM MTE tags memory regions to detect use-after-free and buffer overflow
• Pointer authentication: ARM PAC cryptographically signs pointers to prevent corruption
• Control-flow enforcement: Intel CET prevents return-oriented programming attacks
• Trusted execution: SGX and TrustZone create isolated execution environments

These extensions address security vulnerabilities that are difficult or impossible to prevent through software alone.

Orthogonality

An orthogonal ISA allows independent choices of operations, addressing modes, and data types. Any operation can be combined with any addressing mode on any data type. Orthogonality simplifies compiler code generation and improves code regularity, though it may increase instruction count if some combinations are rarely used.

Completeness

The ISA must support all operations needed for general-purpose computing, including:

• Arithmetic: Basic operations plus multiplication and division
• Logic: AND, OR, XOR, NOT, shifts, rotates
• Data movement: Register-to-register, load, store
• Control flow: Conditional and unconditional branches, subroutine calls
• System operations: Interrupt handling, privileged operations

Missing operations must be synthesized from available instructions, potentially impacting performance.

Implementability

The ISA must be efficiently implementable across a range of performance and power targets:

• Simple implementations: Low-cost embedded processors
• High performance: Out-of-order superscalar desktop and server processors
• Low power: Mobile and battery-powered devices
• High throughput: Heavily pipelined or parallel implementations

An ISA that prevents efficient implementation in any target market limits the architecture's commercial success.

Extensibility

Successful instruction sets evolve over decades. The ISA must accommodate future extensions:

• Reserved encodings: Undefined instruction patterns reserved for future use
• Extension mechanisms: Prefixes, escape codes, or modular extension spaces
• Feature discovery: Software mechanisms to detect available extensions
• Backward compatibility: New processors run old code, old processors trap on new instructions

RISC-V explicitly reserves large encoding spaces for custom and future standard extensions, planning for decades of evolution.

x86 and x86-64

Intel's x86 architecture dominates personal computing and servers:

• CISC heritage: Variable-length instructions, complex addressing modes
• Backward compatibility: Modern processors run code from the 1980s
• Extensive extensions: SSE, AVX, AVX-512 for SIMD; AES-NI for cryptography
• 64-bit extension: AMD64/Intel 64 adds 64-bit registers and addressing

ARM

ARM architecture dominates mobile and increasingly challenges x86 in other markets:

• RISC design: Fixed-width 32-bit instructions (A32) or variable 16/32-bit (Thumb)
• Power efficiency: Designed for battery-powered devices
• AArch64: Clean 64-bit architecture with larger register file
• Rich ecosystem: Extensive licensee implementations from tiny microcontrollers to server processors

RISC-V

The open-source RISC-V architecture provides a modern, clean design:

• Open standard: Freely implementable without licensing fees
• Modular design: Base integer ISA plus optional standard extensions
• Clean slate: No backward compatibility constraints, incorporating lessons learned
• Extensibility: Reserved space for custom extensions

Other Architectures

Additional significant architectures include:

• IBM POWER: High-performance server architecture
• MIPS: Influential RISC architecture, now focusing on embedded applications
• SPARC: Sun's RISC architecture, influential in early workstations
• LoongArch: Chinese-developed architecture for domestic production