Electronics Guide

Synchronous vs. Asynchronous Communication

Serial protocols fall into two broad categories based on their timing approach. Synchronous protocols use a dedicated clock signal to coordinate data transmission, ensuring the receiver samples data at precisely the right moment. The clock signal may be provided by the master device (as in SPI) or embedded within the data stream through encoding techniques.

Asynchronous protocols eliminate the separate clock line by incorporating timing information into the data frame itself. Both transmitter and receiver must agree on the data rate (baud rate), and special start and stop bits frame each data word to enable synchronization. While asynchronous protocols simplify wiring, they require accurate local oscillators and limit maximum data rates.

Full-Duplex, Half-Duplex, and Simplex

Communication directionality defines another fundamental characteristic. Full-duplex protocols support simultaneous bidirectional communication through separate transmit and receive paths. Half-duplex protocols share a single communication path, requiring devices to take turns transmitting. Simplex protocols support one-way communication only, suitable for applications like sensor data streaming.

Single-Ended vs. Differential Signaling

The electrical signaling method significantly impacts noise immunity and maximum cable length. Single-ended signaling references signals to a common ground, making it susceptible to ground loops and electromagnetic interference. Differential signaling uses paired conductors carrying complementary signals, with the receiver detecting the voltage difference between them. This common-mode rejection enables reliable communication over longer distances and in electrically noisy environments.

RS-232 Characteristics

RS-232 originated in the 1960s for connecting data terminal equipment (DTE) to data communication equipment (DCE). It uses single-ended signaling with voltage levels between +3V to +15V representing logic 0 (space) and -3V to -15V representing logic 1 (mark). The inverted logic and wide voltage swing provided noise margin for the technology of its era.

Standard RS-232 connections include transmit data (TXD), receive data (RXD), and various handshaking signals like Request to Send (RTS), Clear to Send (CTS), Data Terminal Ready (DTR), and Data Set Ready (DSR). Modern implementations often use only TXD, RXD, and ground, relying on software flow control (XON/XOFF) when needed.

The standard specifies maximum cable lengths of approximately 15 meters at 20 kbps, though practical implementations often exceed this with quality cables. RS-232 supports point-to-point connections only, limiting its use in multi-device systems.

RS-485 Characteristics

RS-485 addresses RS-232's limitations through differential signaling and multi-drop capability. Using balanced transmission on a twisted pair, RS-485 achieves common-mode rejection ratios exceeding 70 dB, enabling reliable communication over 1200 meters at 100 kbps or shorter distances at rates up to 10 Mbps.

The multi-point capability allows up to 32 unit loads on a single bus segment, with high-impedance receivers enabling even more devices. The half-duplex nature requires direction control, typically managed by asserting a driver-enable signal during transmission. Full-duplex operation requires four wires (two differential pairs).

Proper RS-485 implementation requires attention to termination, biasing, and driver timing. Termination resistors matching the cable characteristic impedance (typically 120 ohms) prevent reflections at high speeds. Bias resistors ensure a known idle state when no device is transmitting.

RS-422

RS-422 provides differential signaling for point-to-point or multi-drop (single transmitter, multiple receivers) applications. It shares RS-485's electrical characteristics but does not support multi-point configurations with multiple transmitters. RS-422 finds use where differential signaling benefits are needed without multi-master requirements.

UART Frame Format

A standard UART frame begins with a start bit (logic low), followed by 5 to 9 data bits (least significant bit first), an optional parity bit for error detection, and one or two stop bits (logic high). The line idles high between frames, allowing the start bit's falling edge to trigger reception.

Common configurations include 8N1 (8 data bits, no parity, 1 stop bit) and 7E1 (7 data bits, even parity, 1 stop bit). The choice depends on application requirements for data width and error detection capability.

Baud Rate and Bit Timing

Baud rate specifies the number of signal transitions per second, equivalent to bits per second in binary systems. Standard rates include 9600, 19200, 38400, 57600, 115200, and higher. Both communicating devices must use identical baud rates, typically derived from crystal oscillators with accuracy better than 2% to prevent framing errors.

Receivers typically oversample the incoming signal (often 16x the baud rate) and use majority voting to determine bit values, improving noise immunity and tolerance for clock differences.

Flow Control

Flow control prevents buffer overflow when the receiver cannot process data fast enough. Hardware flow control uses RTS/CTS signals, where the receiver deasserts CTS to pause transmission. Software flow control embeds XON (0x11) and XOFF (0x13) characters in the data stream, requiring transparent data paths and adding complexity for binary data transmission.

UART Variations

Enhanced UART implementations add features for improved performance and functionality. Multi-processor communication modes use the 9th data bit to distinguish address bytes from data bytes. Auto-baud detection measures incoming signal timing to automatically determine the baud rate. LIN (Local Interconnect Network) UART adds break detection and synchronization features for automotive applications.

SPI Signal Lines

The basic SPI interface uses four signals: Serial Clock (SCLK or SCK) generated by the master, Master Out Slave In (MOSI) carrying data from master to slave, Master In Slave Out (MISO) carrying data from slave to master, and Slave Select (SS or CS) enabling individual slaves. The master controls all timing through the clock signal.

Alternative naming conventions exist, with some documentation using SDI/SDO (Serial Data In/Out) from the device's perspective. Recent standardization efforts promote controller/peripheral and COPI/CIPO (Controller Out Peripheral In) terminology.

Clock Polarity and Phase

SPI defines four modes based on clock polarity (CPOL) and clock phase (CPHA). CPOL determines the clock's idle state (low for CPOL=0, high for CPOL=1). CPHA determines whether data is sampled on the first clock edge (CPHA=0) or second clock edge (CPHA=1). Both master and slave must use matching modes.

Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1) are most common, sampling data on the rising edge. Mode 1 (CPOL=0, CPHA=1) and Mode 2 (CPOL=1, CPHA=0) sample on the falling edge. Device datasheets specify supported modes, and some peripherals support multiple modes.

Multi-Slave Configurations

Multiple slaves connect to a common SPI bus through individual slave select lines. The master asserts only one SS at a time, with unselected slaves presenting high-impedance outputs on MISO. This requires additional GPIO pins for each slave but ensures clean bus arbitration.

Daisy-chain configurations connect slaves in series, with each slave's output feeding the next slave's input. The master shifts data through all slaves sequentially. This topology reduces pin count but increases latency and requires all slaves to participate in every transaction.

SPI Variants

Dual SPI (DSPI) and Quad SPI (QSPI) multiply data throughput by using multiple data lines simultaneously. Flash memory devices commonly support these enhanced modes, achieving effective data rates several times higher than standard SPI at the same clock frequency.

QSPI typically operates in single-bit mode for commands, then switches to four-bit mode for data transfer. Memory-mapped QSPI interfaces in microcontrollers allow executing code directly from external flash.

I2C Bus Structure

I2C uses two bidirectional lines: Serial Data (SDA) and Serial Clock (SCL). Both lines require pull-up resistors, as devices can only pull lines low (open-drain configuration). This wired-AND arrangement enables multi-master operation and clock stretching. Typical pull-up values range from 1k to 10k ohms, depending on bus capacitance and speed requirements.

Each device has a unique 7-bit or 10-bit address. The master initiates transactions by generating a start condition (SDA falling while SCL is high), followed by the slave address and a read/write bit. The addressed slave responds with an acknowledge bit, and data transfer proceeds byte-by-byte with acknowledges.

I2C Speed Modes

Standard mode operates at up to 100 kbps, suitable for most sensor and EEPROM applications. Fast mode extends this to 400 kbps, while Fast mode Plus reaches 1 Mbps. High-speed mode achieves 3.4 Mbps using a current-source pull-up and simplified protocol. Ultra-fast mode specifies 5 Mbps push-pull unidirectional operation.

Bus capacitance limits maximum speed, with the specification allowing 400 pF for standard and fast modes. Longer buses or more devices reduce achievable speeds, requiring careful analysis in complex systems.

Clock Stretching

Slaves can hold SCL low to pause the master when they need additional processing time. This clock stretching feature ensures slower devices can participate on the same bus as faster devices. Masters must monitor SCL and wait for it to release before proceeding. Some simplified master implementations do not support clock stretching, requiring careful device selection.

SMBus

The System Management Bus (SMBus) builds on I2C with additional specifications for system management applications. SMBus defines stricter timing requirements, mandatory timeout detection, and standardized commands for battery management, temperature monitoring, and power control.

Key SMBus additions include the Alert Response Address (ARA) for interrupt-driven communication, the Packet Error Code (PEC) for data integrity, and defined electrical characteristics optimized for system management ICs. While largely compatible with I2C, some timing differences can cause interoperability issues.

PMBus

The Power Management Bus extends SMBus specifically for digital power management. PMBus defines standard commands for configuring and monitoring power converters, enabling interoperable power systems from multiple vendors. Features include output voltage programming, current limiting, telemetry, and sequencing control.

1-Wire Operation

Communication occurs through precisely timed pulse sequences. A master initiates transactions with a reset pulse (480 microseconds low), and slaves respond with presence pulses. Data bits are written and read through time slots, with the master pulling the line low and either holding (write 0) or releasing (write 1) based on the bit value.

Each 1-Wire device contains a unique 64-bit ROM code, enabling enumeration and individual addressing of multiple devices on the same bus. The search algorithm efficiently discovers all devices despite initially unknown addresses.

Parasitic Power

1-Wire devices can derive power from the data line through internal diodes and capacitors, eliminating separate power connections. During communication idle periods, the bus idles high, charging the device's internal capacitor. Active operation draws from this stored energy. Some devices require a strong pull-up (lower resistance or active drive) during high-current operations like EEPROM programming or temperature conversion.

MIPI CSI (Camera Serial Interface)

CSI-2 provides a high-bandwidth interface between image sensors and processors. It uses differential signaling (D-PHY or C-PHY physical layer) with one clock lane and multiple data lanes. Data rates reach 2.5 Gbps per lane with D-PHY and higher with C-PHY, supporting modern high-resolution sensors.

The protocol supports multiple virtual channels, allowing simultaneous transmission from multiple image sources. Embedded synchronization codes mark frame and line boundaries within the continuous data stream.

MIPI DSI (Display Serial Interface)

DSI connects processors to display panels, replacing parallel RGB interfaces with fewer high-speed differential pairs. Like CSI, DSI uses D-PHY or C-PHY signaling and supports multiple data lanes for scalable bandwidth.

DSI operates in command mode (display has internal frame buffer) or video mode (continuous pixel streaming). Video mode includes non-burst, burst, and sync-event timing options to match display requirements. The bidirectional capability enables reading display status and configuration registers.

MIPI I3C

I3C (Improved Inter-Integrated Circuit) modernizes I2C while maintaining backward compatibility. I3C adds push-pull data output for faster speeds (up to 12.5 Mbps), in-band interrupts eliminating dedicated interrupt lines, and dynamic address assignment reducing system configuration complexity.

The protocol supports hot-join of new devices and provides standardized device information for automatic configuration. I3C is gaining adoption for sensor connectivity in mobile and IoT applications.

CAN (Controller Area Network)

CAN has become the dominant in-vehicle network for powertrain, body, and chassis systems. Developed by Bosch in the 1980s, CAN uses differential signaling on a twisted pair with non-destructive bitwise arbitration enabling multi-master operation without collisions.

The protocol supports two frame formats: standard (11-bit identifier) and extended (29-bit identifier). Message priority is determined by identifier value, with lower values having higher priority. This inherent prioritization ensures time-critical messages always win arbitration.

CAN's robust error detection includes CRC checks, bit stuffing, and multiple error counters. Nodes detecting errors transmit error frames, causing all nodes to discard the corrupted message and the transmitter to retry. Error-passive and bus-off states prevent faulty nodes from disrupting the network.

Classical CAN operates at up to 1 Mbps, while CAN FD (Flexible Data-rate) increases payload from 8 to 64 bytes and allows faster bit rates during the data phase (up to 8 Mbps). CAN XL further extends capabilities for emerging automotive requirements.

LIN (Local Interconnect Network)

LIN provides a low-cost alternative to CAN for less critical subsystems like door modules, seat controls, and climate systems. Using single-wire communication with a UART-based physical layer, LIN reduces component costs while providing adequate performance for slower-speed applications.

LIN operates as a master-slave network with one master coordinating all communication. The master sends header frames containing synchronization breaks and protected identifiers, and addressed slaves respond with data. This deterministic scheduling ensures predictable timing for all messages.

FlexRay

FlexRay addresses high-speed, fault-tolerant requirements for advanced chassis control and drive-by-wire systems. Operating at 10 Mbps per channel with optional dual redundant channels, FlexRay provides deterministic timing through a time-triggered communication schedule.

The protocol combines static (time-triggered) and dynamic (event-triggered) segments in each communication cycle. Static slots guarantee bandwidth for periodic messages, while the dynamic segment handles asynchronous data. Clock synchronization maintains tight timing across all nodes without a dedicated master.

Automotive Ethernet

100BASE-T1 and 1000BASE-T1 bring Ethernet to automotive applications using single twisted-pair cabling. These standards meet automotive EMC requirements while enabling the high bandwidth needed for advanced driver assistance systems (ADAS), infotainment, and vehicle diagnostics. Time-Sensitive Networking (TSN) extensions add deterministic timing for critical applications.

Modbus

Modbus, introduced by Modicon in 1979, remains one of the most widely used industrial protocols due to its simplicity and openness. The protocol defines a master-slave architecture with read and write operations on coils (discrete outputs), discrete inputs, input registers, and holding registers.

Modbus RTU uses binary encoding over RS-232 or RS-485 with CRC error checking. Modbus ASCII uses printable characters with LRC checking, sacrificing efficiency for easier debugging. Modbus TCP/IP encapsulates the protocol in TCP packets for Ethernet networks.

Register addressing follows a simple numerical scheme, making Modbus straightforward to implement and debug. However, the lack of device discovery, limited data types, and polling-based architecture present challenges in modern systems.

Profibus

Profibus (Process Field Bus) provides deterministic communication for factory automation and process control. Profibus DP (Decentralized Peripherals) connects controllers to distributed I/O and drives, while Profibus PA (Process Automation) serves intrinsically safe process instrumentation.

The protocol uses a token-passing scheme among masters with cyclic polling of slaves. This hybrid approach combines deterministic timing with multi-master capability. Profibus DP achieves 12 Mbps over RS-485, while Profibus PA uses lower-speed, intrinsically safe signaling compatible with HART infrastructure.

Other Industrial Protocols

DeviceNet layers the CIP (Common Industrial Protocol) on CAN physical layer for discrete manufacturing applications. CANopen provides another CAN-based protocol with standardized device profiles for motion control, I/O, and other device types.

Industrial Ethernet protocols including EtherNet/IP, PROFINET, and EtherCAT bring high-speed deterministic communication to modern automation systems, often with time-synchronization and motion-control extensions.

Data Rate Requirements

Required bandwidth determines viable protocol options. Low-speed sensors may need only I2C or 1-Wire, while high-resolution displays demand MIPI DSI. Consider not just average throughput but peak requirements and timing constraints.

Distance and Environment

Communication distance strongly influences protocol choice. On-board connections between ICs can use any protocol, while long factory runs favor RS-485 or industrial Ethernet. Electrically noisy environments benefit from differential signaling and robust error handling.

Device Count and Topology

Single peripheral connections suit SPI or point-to-point UART. Multiple devices on a shared bus require I2C, CAN, or other multi-drop protocols. Consider address space limitations and bus loading effects.

Power and Cost Constraints

Battery-powered applications favor protocols with low-power modes. Cost-sensitive designs minimize driver ICs and connector pins. Protocols like 1-Wire and I2C minimize wiring complexity.

Ecosystem and Tool Support

Available devices, development tools, and debugging equipment influence practical protocol choices. Popular protocols benefit from extensive device selection and mature analysis tools.

Signal Integrity

High-speed signals require attention to transmission line effects. Match trace impedances, minimize stubs, and provide proper termination. Differential pairs should be routed with matched lengths and consistent spacing. Ground planes under signal traces improve return paths and reduce EMI.

Error Handling

Implement robust error detection using protocol-provided mechanisms (CRC, parity, acknowledges) and add application-level verification where appropriate. Design retry mechanisms with appropriate backoff to prevent error storms. Log errors for system diagnostics.

Timing Margins

Verify timing margins across temperature, voltage, and production variations. Include guard time around setup and hold requirements. Characterize cable and connector delays for long-distance links.

EMC Considerations

Serial interfaces can both emit and receive electromagnetic interference. Use proper filtering on cables leaving enclosures. Shield cables for sensitive applications. Consider common-mode chokes for differential interfaces.