Electronics Guide

Clock-Synchronized Acquisition

In state mode, the logic analyzer samples all input channels whenever the specified clock signal meets a defined condition, typically a rising or falling edge. This synchronization ensures that captured data reflects valid logic levels, sampled during the stable portion of each clock cycle when signals have settled.

The clock source can be any signal from the target system: a system clock, a bus strobe, a chip select, or any other timing reference. Some measurements require multiple clocks, such as when analyzing transactions between clock domains or capturing different phases of a complex bus protocol.

Clock qualification allows conditional sampling based on additional signals. For example, the analyzer might sample data only when a chip select is active, filtering out irrelevant clock cycles and focusing memory on meaningful transactions. This technique effectively extends capture depth by excluding uninteresting data.

State Display Formats

State analysis data appears in tabular format, with each row representing one sampled state and columns showing channel groups. The display resembles a spreadsheet of captured values, making it easy to trace the sequence of operations.

Numeric formats allow viewing data as hexadecimal, binary, octal, decimal, or ASCII values. Channel groups can be named and formatted independently, so an address bus might display in hexadecimal while a status register shows individual bit names.

Symbols and labels replace numeric values with meaningful names. By loading symbol tables from the target system's software build, addresses can display as function names, memory locations can show variable names, and register values can decode to their defined meanings. This symbolic view dramatically accelerates understanding of captured data.

State listing navigation provides search and filter capabilities to locate specific patterns, values, or conditions within potentially millions of captured states. Engineers can jump between occurrences of specific addresses, find transactions involving particular data values, or filter the display to show only selected types of operations.

Setup and Hold Time Considerations

Proper state analysis requires that input signals meet the logic analyzer's setup and hold time requirements relative to the clock edge. If signals transition too close to the sampling clock, the analyzer may capture incorrect values or exhibit metastability.

Modern logic analyzers specify setup and hold windows of a few nanoseconds or less. When these specifications cannot be met by the target system, adjustable sample positions allow moving the sampling point within the clock period to find a stable region where all signals have settled.

Some instruments provide eye finder or auto-deskew features that automatically determine optimal sampling points by analyzing signal transitions relative to the clock. These tools measure the actual setup and hold margins on each channel, ensuring reliable data capture.

Asynchronous Sampling

In timing mode, the instrument samples all channels at a fixed rate determined by its internal timebase, independent of any system clock. Sample rates range from megahertz in basic analyzers to tens of gigahertz in high-performance instruments. Higher sample rates provide finer timing resolution but consume memory faster.

The sampling theorem requires sampling at least twice the highest frequency component of interest. For digital signals, this means the sample rate should be at least twice the fastest edge rate to accurately capture transition times. In practice, higher oversampling ratios of five to ten times provide more accurate timing measurements.

Transitional timing or transitional sampling stores samples only when signals change, dramatically extending effective capture depth. Instead of recording every sample, the analyzer stores the sample value and a timestamp for each transition. This compression allows capturing long time spans while preserving the timing of every edge.

Timing Display and Measurement

Timing data displays as waveforms similar to an oscilloscope display, but showing logic levels rather than analog voltages. Multiple channels appear as parallel waveform traces, with high and low states clearly distinguished. Bus groups can display as composite waveforms with numeric values shown between transitions.

Cursor measurements quantify timing relationships between any two points in the captured data. Cursors can measure the time between edges on the same channel (pulse width) or between edges on different channels (propagation delay, setup time). Automatic measurements calculate statistics across all occurrences of specified timing relationships.

Zoom and scroll controls allow examining captured data at various time scales, from the overview of the entire acquisition to fine detail of individual edges. The deep memory of modern analyzers means captured data may span milliseconds while individual transitions occur in nanoseconds, requiring extensive zoom range.

Glitch Capture

Glitches are narrow pulses that may indicate noise, race conditions, or other signal integrity problems. Because glitches can be shorter than the sample period, they may not appear in normal timing captures. Dedicated glitch detection circuitry identifies these brief excursions.

Glitch capture modes use specialized hardware to detect transitions between sample points. When a glitch is detected, it is marked in the captured data even though conventional sampling missed it. Some analyzers store glitches with partial timing information, while others simply flag their occurrence.

Analyzing glitches often requires correlating the glitch detection with detailed timing capture. Once a glitch is identified, the analyzer can trigger on that condition and capture surrounding context to understand what caused the brief signal excursion.

Basic Pattern Triggering

The simplest trigger condition is a pattern match: the analyzer triggers when a specified combination of logic levels appears on the input channels. Patterns can specify each channel as high, low, or don't-care (either state acceptable).

Edge triggering extends pattern matching to include signal transitions. The analyzer triggers on the rising or falling edge of specified signals, optionally qualified by patterns on other channels. This combination captures events like a specific address appearing when a write strobe occurs.

Pattern duration triggers require that a pattern remain stable for a specified time before triggering. This capability distinguishes between momentary glitches and sustained conditions, capturing only events where signals remain in a particular state long enough to be significant.

Sequential Triggering

Sequential triggers define a series of conditions that must occur in order before the analyzer triggers. Each stage specifies a pattern or event, and the trigger system advances through stages only when conditions are met. This capability isolates specific sequences from the many similar patterns that might occur.

A sequence trigger might specify: find pattern A, then within 100 microseconds find pattern B, then on the next occurrence of pattern C, trigger. This three-stage sequence could identify a specific error condition that occurs only after a particular initialization sequence.

Branch conditions in advanced trigger systems allow conditional paths through the sequence. If condition X occurs, proceed to stage 3; if condition Y occurs instead, restart the sequence. This programming flexibility handles complex protocols where multiple paths lead to the event of interest.

Counters and timers within the trigger system enable conditions like trigger after the 15th occurrence of a pattern or trigger if pattern B does not occur within 50 microseconds of pattern A. These quantitative conditions are essential for debugging intermittent failures that occur only after many repetitions or timeout conditions where expected events fail to occur.

Advanced Trigger Features

Trigger position determines where in the acquisition memory the trigger point falls. Pre-trigger capture stores data from before the trigger, showing what led up to the event. Post-trigger capture stores data after the trigger, showing consequences. Variable trigger position allows any mix, from all pre-trigger to all post-trigger.

Trigger holdoff prevents re-triggering for a specified time after each trigger. This feature is useful when the trigger condition occurs multiple times in succession but only the first occurrence is of interest.

Trigger output generates a signal when the trigger condition is met. This output can synchronize other instruments, mark oscilloscope captures, or provide timing references. Conversely, trigger input allows external events to trigger the logic analyzer, coordinating acquisition with events detected by other equipment.

Data qualification specifies conditions under which captured data is stored in memory. Unlike triggering, which determines when capture begins, qualification determines which samples are stored during capture. Qualifying on a chip select, for example, stores only cycles where the selected device is active.

Serial Protocol Analysis

Serial protocols transmit data one bit at a time over a small number of wires. Common serial protocols decoded by logic analyzers include SPI, I2C, UART, CAN, LIN, and many others. Each protocol requires specific understanding of framing, addressing, and data encoding.

SPI (Serial Peripheral Interface) decoding identifies clock, data, and chip select signals to extract transmitted bytes. The decoder shows master-out and slave-in data aligned, making bidirectional transactions clear. Configuration options handle various clock polarities and data phase relationships.

I2C (Inter-Integrated Circuit) decoding interprets the two-wire protocol's start conditions, address phases, acknowledgments, and data bytes. The decoder distinguishes read from write transactions, identifies addressed devices, and flags protocol errors like missing acknowledgments.

UART (Universal Asynchronous Receiver/Transmitter) decoding extracts data from asynchronous serial streams using specified baud rates, data bits, and parity settings. The decoder reassembles characters and can display results as hex values, decimal, or ASCII text depending on the application.

Higher-speed serial protocols like USB, PCIe, and SATA require specialized protocol analyzers due to their multi-gigabit data rates and complex protocol stacks. However, control and management signals associated with these interfaces often remain within logic analyzer bandwidth and benefit from decoding.

Parallel Bus Analysis

Parallel buses transmit multiple bits simultaneously across separate conductors. Memory buses, processor buses, and parallel peripheral interfaces all benefit from protocol decoding that interprets address, data, and control signals together.

Memory bus decoding shows read and write transactions with addresses and data values. For synchronous memory interfaces, the decoder handles the complex timing of command, address, and data phases that characterize modern DDR memory access.

Processor bus analysis reveals instruction fetches, data access, and I/O operations. By decoding the processor's bus protocol, engineers can trace program execution, identify memory access patterns, and debug hardware/software interactions.

Custom protocol definition allows creating decoders for proprietary or unusual interfaces. By specifying how signals combine to indicate transaction boundaries, data encoding, and field meanings, engineers extend protocol decoding to application-specific buses.

Protocol Error Detection

Protocol decoders identify violations of protocol rules, flagging errors that might otherwise go unnoticed in raw waveform data. These errors often indicate hardware problems, software bugs, or interoperability issues between devices.

Framing errors occur when start and stop conditions or synchronization patterns are missing or malformed. Timing violations flag when signal transitions occur outside specified windows. Protocol sequence errors identify illegal state transitions or missing required phases.

Error highlighting in the decoded display draws attention to problems. Engineers can configure triggers to capture only transactions containing errors, focusing acquisition memory on problematic events rather than normal operation.

Memory Architecture

Logic analyzer memory stores samples from all channels for later analysis. Memory depth, specified in samples or time at maximum sample rate, determines how long an acquisition window the analyzer can capture. Deep memory allows capturing rare events without missing context.

Per-channel memory allocates a fixed amount of storage to each input channel. This architecture simplifies hardware but may waste memory when fewer channels are needed. Shared memory architectures allocate a common pool to active channels, allowing deeper captures when fewer channels are configured.

Segmented memory divides total memory into multiple segments, each capturing data around a separate trigger event. This approach captures many occurrences of an event without storing the irrelevant data between occurrences, effectively multiplying useful capture depth.

Sample Rate and Bandwidth

Sample rate determines timing resolution and limits the frequency of signals that can be accurately captured. Higher sample rates provide finer timing detail but consume memory faster, reducing the capture window at a given memory depth.

Maximum sample rate is achieved only when using a limited number of channels on most instruments. As more channels are activated, the sample rate typically decreases because the same acquisition resources are shared among more inputs. Specification sheets should be consulted to understand the sample rate available for a given channel configuration.

Timing resolution equals the reciprocal of the sample rate. A 1 GHz sample rate provides 1 nanosecond resolution, meaning edge placements are known only to within one sample period. Interpolation techniques can improve apparent resolution but cannot recover information not present in the samples.

Acquisition Modes

Single acquisition captures one buffer of data and stops, providing a snapshot of system behavior at one moment. This mode suits most debugging tasks where a single event needs detailed examination.

Repetitive acquisition continuously captures and overwrites memory until stopped or a trigger occurs. This mode allows watching live system behavior while waiting for a specific event to occur, at which point the capture freezes for analysis.

Sequence acquisition captures multiple segments, each triggered independently. The analyzer can accumulate thousands of trigger events over hours or days, later allowing analysis of each captured segment. This mode is invaluable for capturing rare intermittent problems.

Transitional Storage

Transitional storage records only samples where at least one channel changes state. Each stored sample includes a timestamp indicating when the transition occurred. This lossless compression preserves all timing information while dramatically reducing storage requirements for signals with low transition rates.

The compression ratio depends on signal activity. Signals that change on every sample see no benefit, while signals with occasional transitions achieve compression ratios of 100:1 or higher. Most digital systems have many signals that remain stable for long periods, making transitional storage highly effective.

Minimum pulse width in transitional mode determines the narrowest pulse guaranteed to be captured. Very brief glitches between samples might not create stored transitions. Specifications should be consulted to understand the trade-offs between compression and minimum captured pulse width.

Periodic Storage

Periodic storage captures samples at regular intervals less than the maximum sample rate, reducing data volume proportionally. This approach trades timing resolution for longer capture windows, appropriate when precise edge timing is less important than observing long-term behavior.

Demultiplexed modes allow using multiple physical channels to capture one logical channel at an effective sample rate higher than any single channel. By interleaving samples across channels, the analyzer achieves higher timing resolution on critical signals at the cost of reduced channel count.

Selective Storage

Selective storage uses trigger-like conditions to control which samples are stored rather than just when storage begins. Only samples meeting specified conditions consume memory, focusing storage on relevant data.

This technique is particularly useful for filtering bus transactions. By storing only accesses to specific address ranges or only operations matching particular patterns, acquisition memory concentrates on the subset of activity relevant to the current investigation.

Combining selective storage with transitional storage and deep memory creates instruments capable of capturing hours of system activity while preserving full timing detail for every relevant event.

Probe Types

Flying lead probes consist of individual wires terminating in grabber clips or probe tips. These versatile probes connect to any accessible point on a circuit board, including component leads, test points, and via pads. Flying leads work well for prototype debugging but become unwieldy for high channel counts.

Compression connectors make simultaneous contact with many points through spring-loaded pins or elastomeric contacts. These probes connect to footprints designed into the target board, providing reliable high-channel-count connections. Headers matching common debug connector standards simplify mechanical attachment.

Interposer probes insert between a component and its socket, providing access to all component pins without board modifications. These specialized probes suit processor and memory debugging where signals are not otherwise accessible. High-performance interposers maintain signal integrity despite the added interconnect.

Solder-down headers are permanently attached to target boards, providing reliable, low-profile connections. While requiring board modifications, these headers offer excellent signal quality and mechanical security for production test or extended debugging.

Signal Integrity Considerations

Input capacitance of the probe loads the target signal, potentially affecting rise times and causing reflections on transmission lines. Lower capacitance probes minimize these effects, with modern probes achieving capacitance values below 1 picofarad.

Ground connection quality profoundly affects measurement accuracy at high frequencies. Long ground leads add inductance that causes ringing and overshoot in the observed signal, even when the actual signal is clean. Short, direct ground connections closest to the signal point provide the most accurate measurements.

Probe bandwidth must exceed the fastest edge rates in the target system. A probe with insufficient bandwidth rounds the edges of fast signals, making timing measurements inaccurate. High-bandwidth probes use careful impedance control and low-inductance construction to preserve signal fidelity.

Threshold Levels

Logic analyzers compare input signals against voltage thresholds to determine logic states. Threshold settings must match the logic family being probed to correctly distinguish high and low states.

Common threshold settings include TTL (1.5 V), CMOS (half of VCC), LVCMOS (various levels from 0.8 V to 1.65 V), and differential standards like LVDS. Mismatched thresholds cause incorrect state detection, appearing as spurious transitions or stuck signals.

User-defined thresholds allow setting arbitrary voltage levels to match unusual logic levels or to deliberately sample signals at specific points on their transitions. This flexibility accommodates custom designs and enables specialized measurements like eye diagram analysis.

Symbol Loading

Symbol files generated during software compilation contain the mapping between addresses and source code elements. Loading these files into the logic analyzer allows replacing numeric addresses with function names, variable names, and file/line references.

Common symbol file formats include ELF (used by many embedded toolchains), DWARF debugging information, and various proprietary formats from chip and tool vendors. Logic analyzer software reads these formats and extracts the symbol-to-address mappings.

With symbols loaded, the state listing shows function names instead of hexadecimal addresses for instruction fetches. Data accesses show variable names. Stack traces reconstruct the call sequence leading to captured events. This symbolic view transforms cryptic numbers into understandable program context.

Source Code Display

Integrated source code windows display the actual source files with highlighting indicating which lines correspond to captured events. Clicking on a line in the source view navigates to that point in the acquisition; clicking in the acquisition view highlights the corresponding source line.

This bidirectional navigation dramatically accelerates debugging. When an unexpected hardware event appears in the capture, one click reveals the software instruction that caused it. When investigating why code did not behave as expected, the capture shows exactly what hardware operations actually occurred.

Execution profiling uses correlation data to measure how long each function or code region executes. By correlating addresses of captured instructions with the source structure, the analyzer builds profiles showing where time is spent, identifying optimization opportunities and unexpected latencies.

Trace Reconstruction

Modern processors provide trace ports that output compressed execution information. Logic analyzers with trace support capture this data and reconstruct the complete instruction-by-instruction execution sequence.

ARM CoreSight trace provides execution flow information through Embedded Trace Macrocell (ETM) outputs. By capturing the trace port signals and decoding them with knowledge of the program image, the analyzer reconstructs which instructions executed and in what order.

Instruction trace shows every instruction executed, enabling stepping backward through execution to understand how the processor reached any captured state. Combined with data trace information, engineers see not just what instructions executed but what data values were involved.

Trace triggering extends the trigger system to include software events. Triggers can fire on entry to specific functions, access to particular variables, or execution of exact code sequences. These software-aware triggers isolate relevant captures from the millions of instructions that execute in complex systems.

Analog and Digital Correlation

Correlating analog and digital views reveals how analog conditions affect digital behavior and vice versa. Power supply droops, reference voltage variations, and clock jitter are analog phenomena that cause digital failures. Seeing both domains simultaneously on a common time scale shows these cause-and-effect relationships.

Time-correlated displays show oscilloscope channels and logic analyzer channels aligned to the same time base. Cursors and measurements span both channel types, quantifying timing relationships between analog transitions and digital events.

Cross-domain triggering allows analog conditions to trigger digital acquisition or digital patterns to trigger analog capture. An oscilloscope trigger on power supply glitches can initiate logic analyzer capture of the resulting digital errors. A digital trigger on a specific bus transaction can capture the associated analog signal characteristics.

Serial Bus Physical Layer Analysis

Serial buses have both protocol-level behavior (decoded by logic analyzers) and physical-layer characteristics (analyzed by oscilloscopes). Mixed-signal instruments examine both aspects, revealing whether problems are in the protocol implementation or the electrical signaling.

Eye diagrams show the analog quality of digital signals by overlaying many bit periods. The eye opening indicates margin against noise and timing jitter. Logic analyzer decoding identifies which protocol elements correspond to poor eye quality.

Physical layer measurements including rise time, overshoot, and jitter complement protocol decode to provide complete bus characterization. When protocol errors occur, physical layer examination reveals whether the root cause is signal integrity or logic design.

Embedded Systems Debug

Embedded systems combine processors, peripherals, and software in tightly integrated designs. Logic analyzers observe the processor bus, peripheral interfaces, and I/O signals simultaneously, revealing how software and hardware interact.

Debugging embedded systems often requires correlating software execution with hardware events. When an interrupt is missed or a peripheral misbehaves, the logic analyzer shows the exact sequence of operations, the timing of signals, and the software instructions involved.

Communication between processor and peripherals over serial buses like SPI and I2C is a common source of problems. Protocol decode reveals whether commands are correctly formed, responses are properly received, and timing meets specifications.

FPGA Development

FPGA designs present debugging challenges because internal signals are not directly accessible. Embedded logic analyzers synthesized within the FPGA provide visibility into internal operation, functioning like a built-in logic analyzer that shares the FPGA fabric.

External logic analyzers complement embedded instruments by observing FPGA I/O pins without consuming internal resources. The combination of internal and external visibility provides a complete picture of FPGA behavior at both internal logic and pin-level interfaces.

State machine debugging benefits from logic analyzer triggering that can wait for specific state sequences. By defining triggers that match the expected state sequence and capturing when deviations occur, engineers isolate exactly where state machines misbehave.

Hardware Validation

Validating hardware designs requires verifying that implementations meet timing specifications, protocol requirements, and interoperability standards. Logic analyzers provide the measurements needed for this verification.

Timing margin analysis measures actual setup and hold times and compares them against specifications. By capturing many transactions and measuring timing distributions, engineers verify adequate margins exist across operating conditions.

Protocol compliance testing verifies that bus implementations correctly follow standard specifications. Decoders that flag protocol violations automate much of this testing, identifying any deviations from required behavior.

Interoperability testing connects devices from different sources and verifies they communicate correctly. Logic analyzer captures document the actual signal exchanges, providing evidence for debugging compatibility problems between devices.

Channel Count

The number of channels must accommodate all signals to be observed simultaneously. Count not just data bits but also clock, control, and status signals. Applications range from eight channels for simple serial interfaces to hundreds of channels for processor buses.

Some instruments allow combining multiple units for higher channel counts, though synchronization between units must be verified. Others offer modular architectures where channel cards can be added as needs grow.

Speed and Memory

Sample rate must be sufficient to resolve the fastest edges in the system under test. For timing analysis, a sample rate of at least five times the fastest signal frequency provides reasonable measurements. State analysis has different requirements based on setup and hold specifications.

Memory depth determines the capture window at a given sample rate. Calculate the required capture time and verify the instrument can provide it at the necessary sample rate. Compression features can extend effective depth but should not be relied upon for signals with high transition rates.

Protocol Support

Verify that needed protocol decoders are available, either included with the instrument or as options. Some decoders are available from third parties. Consider both current needs and likely future requirements when evaluating protocol support.

The quality of decoders matters as much as their availability. Evaluate whether decoders provide the level of detail needed, correctly identify errors, and integrate well with the overall analysis workflow.