Electronics Guide

Sampling

Sampling captures the instantaneous value of a continuous signal at specific moments in time. The sampling rate, or sample frequency, determines how often these snapshots occur. The Nyquist-Shannon sampling theorem establishes that a signal can be perfectly reconstructed if sampled at more than twice its highest frequency component. This minimum rate is called the Nyquist rate.

Sampling below the Nyquist rate causes aliasing, where high-frequency components fold back into the signal band, creating artifacts indistinguishable from legitimate signal content. Anti-aliasing filters before the ADC remove frequencies above half the sample rate, preventing this corruption. Practical systems sample significantly above the Nyquist rate to ease anti-aliasing filter requirements.

Quantization

Quantization maps continuous amplitude values to discrete digital codes. An N-bit converter divides the input range into 2^N levels. Each level spans one least significant bit (LSB), equal to the full-scale range divided by 2^N. Input values within each quantization interval map to the same output code.

This rounding introduces quantization error, the difference between actual and represented values. For a properly dithered or sufficiently complex signal, quantization error appears as white noise uniformly distributed over +/-0.5 LSB. The signal-to-quantization-noise ratio (SQNR) improves approximately 6 dB for each additional bit of resolution: a 16-bit converter achieves about 98 dB SQNR theoretically.

Sample-and-Hold

Most ADC architectures require the input signal to remain constant during conversion. A sample-and-hold (or track-and-hold) circuit captures the input value and maintains it while the conversion proceeds. During the tracking phase, the output follows the input; upon receiving a sample command, the circuit holds the instantaneous value.

Sample-and-hold performance affects overall ADC accuracy. Aperture jitter, uncertainty in the exact sampling instant, introduces errors that increase with input frequency. Droop, the decay of held voltage over time, limits how long conversion can take. Many integrated ADCs include sample-and-hold circuits, but high-performance systems may use external components.

Successive Approximation Register (SAR)

SAR ADCs determine the digital output through binary search. Starting with the most significant bit, the converter tests each bit by comparing the input against a DAC-generated reference. If the input exceeds the reference, the bit remains set; otherwise, it clears. This process repeats for each bit, requiring N comparison cycles for N-bit resolution.

SAR converters achieve moderate speed (up to several megasamples per second) with excellent power efficiency and good accuracy. They suit multiplexed data acquisition, sensor interfaces, and battery-powered applications. Resolution typically ranges from 8 to 20 bits. The architecture scales well with process technology, making SAR ADCs increasingly popular in modern designs.

Delta-Sigma (Oversampling)

Delta-sigma ADCs sample at rates far exceeding the signal bandwidth, then use digital filtering to increase resolution. A modulator converts the input to a high-speed, low-resolution bitstream. The oversampling spreads quantization noise across a wide frequency band; digital decimation filters then remove out-of-band noise while reducing the data rate.

Delta-sigma converters excel at high resolution (16-24 bits) for bandwidth-limited signals. Audio ADCs universally use this architecture, achieving 24-bit resolution with exceptional linearity. Industrial measurement, strain gauge interfaces, and precision instrumentation benefit from delta-sigma accuracy. However, the architecture introduces latency from the digital filter, and changing inputs require settling time.

Flash (Parallel)

Flash ADCs perform conversion in a single clock cycle using 2^N-1 comparators, each referenced to a different voltage level. The comparator outputs form a thermometer code converted to binary output. This parallel approach achieves the highest conversion rates, exceeding tens of gigasamples per second.

The large number of comparators limits flash converters to low resolution (typically 6-8 bits) due to power consumption and die size. Flash ADCs suit high-speed oscilloscopes, radar receivers, and optical communication systems where speed matters more than resolution. They also serve as building blocks in pipeline and subranging architectures.

Pipeline

Pipeline ADCs divide conversion into stages, each resolving a few bits and passing a residue to the next stage. This architecture achieves high speed (hundreds of megasamples per second) with moderate resolution (10-16 bits). Digital error correction compensates for stage inaccuracies, relaxing component requirements.

Pipeline converters suit video digitization, communications receivers, and high-speed data acquisition. The multi-stage structure introduces latency (several clock cycles) but maintains throughput of one conversion per clock. Power consumption falls between flash and SAR architectures for similar speed and resolution.

Integrating (Dual-Slope)

Integrating ADCs measure the time required to integrate the input signal to a reference level. Dual-slope converters integrate the input for a fixed time, then integrate a reference in the opposite direction until reaching zero. The ratio of integration times indicates the input value.

This architecture provides excellent noise rejection, particularly for frequencies related to the integration time. Line-frequency rejection makes dual-slope ADCs ideal for digital multimeters and precision DC measurements. However, conversion times measured in milliseconds limit applications to slowly changing signals.

Resolution

Resolution indicates the number of output bits, determining the finest distinction the converter can make. Higher resolution does not guarantee higher accuracy; other error sources may dominate. Effective number of bits (ENOB) provides a more meaningful measure, indicating the resolution achievable given actual noise and distortion.

Sampling Rate

Maximum sampling rate specifies how fast the converter can operate. Some converters allow trading resolution for speed, others operate at fixed rates. The relationship between sampling rate and signal bandwidth determines whether oversampling techniques can improve effective resolution.

Input Range

Input voltage range defines the span of analog voltages the converter can digitize. Signals outside this range saturate at maximum or minimum codes. Common ranges include 0 to reference voltage, +/-reference voltage, and various scaled ranges. Input structure may be single-ended (referenced to ground) or differential (measuring voltage between two inputs).

DC Accuracy

DC accuracy specifications describe errors in converting constant voltages. Offset error indicates the code produced for zero input. Gain error describes the slope difference between ideal and actual transfer functions. Integral nonlinearity (INL) measures maximum deviation from a straight line fit. Differential nonlinearity (DNL) indicates variation in step sizes between adjacent codes.

Dynamic Performance

Dynamic specifications characterize AC signal conversion. Signal-to-noise ratio (SNR) compares signal power to noise power. Signal-to-noise-and-distortion ratio (SINAD) includes harmonic distortion with noise. Total harmonic distortion (THD) measures harmonic content relative to the fundamental. Spurious-free dynamic range (SFDR) indicates the ratio of signal to the largest spurious component.

Effective Number of Bits

ENOB provides a single figure of merit combining noise and distortion effects: ENOB = (SINAD - 1.76) / 6.02. A 12-bit converter might achieve only 10 ENOB due to noise and nonlinearity. ENOB typically degrades at higher frequencies and higher input amplitudes, so specifications often provide ENOB versus frequency plots.

Anti-Aliasing Filters

Anti-aliasing filters remove frequencies above half the sample rate, preventing aliasing. The filter must attenuate out-of-band content to levels below quantization noise. Higher-order filters provide steeper roll-off but add phase distortion and settling time. Oversampling converters relax anti-aliasing requirements by moving the Nyquist frequency well above the signal band.

Driving the ADC Input

ADC inputs present varying loads depending on architecture. SAR converters draw charge pulses that can disturb input voltage if source impedance is too high. Pipeline and delta-sigma inputs may look like switched-capacitor loads. Input buffer amplifiers isolate the signal source from ADC loading effects while providing the low output impedance needed for fast settling.

Reference Quality

ADC accuracy depends critically on reference voltage quality. Reference noise directly adds to converted signal noise. Temperature drift causes gain errors. Reference settling time affects throughput in multiplexed systems. External precision references may be necessary when internal references prove inadequate.

Differential vs. Single-Ended

Differential inputs measure the voltage between two signals, rejecting common-mode noise and interference. This doubles the effective signal swing for given supply voltages and improves noise performance. Differential signaling requires careful signal routing and may need single-ended to differential conversion circuitry.

Power Supply Requirements

ADC power supplies must be clean and well-regulated. Noise on analog supplies directly contaminates conversions. Digital supply noise can couple into analog circuits. Separate filtering and possibly separate regulators for analog and digital supplies prevent digital noise from corrupting measurements. Low-dropout regulators and ferrite beads help isolate sensitive circuitry.

Layout and Grounding

Careful PCB layout preserves ADC performance. Keep analog input traces short and away from digital signals. Provide low-impedance ground returns for both analog and digital circuits. Consider ground plane partitioning to prevent digital currents from flowing through analog ground areas. Follow manufacturer layout guidelines, which often include reference designs.

Clock Quality

Sample clock jitter translates directly to amplitude noise in the converted signal. The effect worsens with input frequency: a 1 ps jitter that is negligible at 1 kHz causes significant error at 100 MHz. High-speed and high-resolution applications require low-jitter clock sources and careful clock distribution.

Calibration

Many ADCs include calibration features to correct offset, gain, and linearity errors. Initial calibration after power-up and periodic recalibration during operation maintain accuracy over temperature and time. System-level calibration using known reference signals can correct errors beyond ADC capabilities.

Audio Recording

Audio applications demand high resolution (24-bit), low distortion, and flat frequency response across the audio band (20 Hz to 20 kHz). Delta-sigma converters dominate, providing excellent linearity and integrated digital filtering. Multi-bit delta-sigma architectures and dynamic element matching ensure low distortion. Sample rates of 44.1, 48, 96, or 192 kHz balance fidelity against data storage requirements.

Data Acquisition

General-purpose data acquisition systems need flexibility to handle diverse signals and scan multiple channels. SAR converters provide good resolution (12-18 bits) with fast channel-to-channel switching. Multiplexing shares one ADC among many channels, though simultaneous sampling requires multiple converters. Programmable gain amplifiers extend dynamic range.

Communications Receivers

Software-defined radio digitizes wide bandwidth signals for digital processing. High sample rates (hundreds of megasamples per second) and moderate resolution (12-16 bits) suit these applications. Pipeline architectures provide the necessary speed. Undersampling techniques alias intentional frequency bands to baseband, simplifying front-end design.

Instrumentation

Precision measurement instruments prioritize accuracy over speed. High-resolution delta-sigma or dual-slope converters provide the necessary precision. Careful analog design, shielding, and calibration achieve accuracy approaching the converter's theoretical limits. Averaging and filtering further improve effective resolution.