Spread-Spectrum Clocking
Spread-spectrum clocking (SSC) is a technique that intentionally modulates a clock signal's frequency to reduce peak electromagnetic emissions. By spreading the clock energy across a wider frequency band rather than concentrating it at a single frequency and its harmonics, SSC significantly reduces the amplitude of radiated and conducted emissions without requiring additional shielding or filtering. This technique has become essential for meeting electromagnetic compatibility (EMC) regulations in modern electronic systems.
The fundamental principle behind spread-spectrum clocking exploits how EMC measurements are performed. Regulatory standards typically measure emissions using a receiver with a specific resolution bandwidth. When clock energy is spread across a frequency range wider than this measurement bandwidth, the detected power at any single frequency decreases proportionally. While the total radiated energy remains essentially unchanged, the peak emissions that determine regulatory compliance are substantially reduced, often by 6 to 20 dB depending on the spreading parameters and measurement conditions.
Modulation Profiles
The modulation profile describes how the instantaneous frequency varies over time as the clock is spread across its frequency range. Different profiles offer distinct trade-offs between EMI reduction effectiveness, timing margin impact, and implementation complexity. Understanding these profiles is essential for selecting the appropriate technique for a given application.
Triangular Modulation
Triangular modulation linearly sweeps the frequency between the minimum and maximum values at a constant rate, producing a symmetric triangle waveform in the frequency domain. This profile is the most common choice due to its simplicity of implementation and reasonably uniform spectral spreading. The linear frequency sweep causes the clock to spend equal time at each frequency within the spread range, resulting in relatively flat spectral distribution across the modulation bandwidth.
The sharp corners of the triangular waveform at the frequency extremes can create small spectral artifacts, but these are typically negligible compared to the overall EMI reduction achieved. Digital implementations of triangular modulation often use simple up-down counters to control the frequency, making this profile attractive for all-digital PLL architectures.
Sinusoidal Modulation
Sinusoidal modulation varies the frequency according to a sine wave, producing a more concentrated spectral energy distribution at the frequency extremes where the rate of change is slowest. While mathematically elegant and naturally free of high-frequency harmonics in the modulation signal itself, sinusoidal profiles result in less uniform spreading compared to triangular modulation.
The frequency spends more time near the maximum and minimum excursions, creating peaks in the spread spectrum at these points. This can reduce the effective EMI reduction at specific frequencies compared to triangular profiles with the same spreading range. However, sinusoidal modulation may be preferred in systems where the smooth frequency transitions reduce other system artifacts.
Hershey-Kiss Profile
The Hershey-Kiss profile, named for its resemblance to the chocolate candy's shape when viewed in the frequency-time domain, represents an optimized modulation waveform designed to maximize spectral flatness. This profile combines the uniform spreading of triangular modulation with modified slopes near the extremes to eliminate the spectral artifacts caused by linear turnarounds.
By reducing the rate of frequency change as the modulation approaches its limits, the Hershey-Kiss profile achieves more uniform energy distribution across the spread bandwidth. This results in improved EMI reduction compared to simple triangular or sinusoidal profiles with the same peak-to-peak frequency deviation. The trade-off is increased implementation complexity, typically requiring lookup tables or polynomial approximations in digital implementations.
Lexicographic Sequences
Advanced spread-spectrum implementations may use pseudo-random or lexicographic sequences to modulate the frequency. Rather than following a deterministic waveform, these approaches select frequency offsets from a predefined set according to a sequence designed to minimize spectral peaks. The resulting spectrum resembles noise within the spread bandwidth, potentially offering improved flatness compared to periodic modulation waveforms.
Lexicographic modulation is particularly useful when avoiding correlation with other system frequencies or when the modulation rate itself might create problematic interference. However, the more complex frequency patterns can complicate timing analysis and may require more sophisticated tracking in downstream PLLs.
Spreading Ratios and Deviation
The spreading ratio, typically expressed as a percentage, defines how much the clock frequency deviates from its nominal value during modulation. This parameter fundamentally determines both the EMI reduction achieved and the impact on system timing. Common spreading ratios range from 0.5% to 2.5%, with 0.5% being typical for high-speed interfaces and 1.5% to 2% common in consumer electronics where maximum EMI reduction is prioritized.
Calculating Frequency Deviation
For a nominal clock frequency of 100 MHz with a 1% spreading ratio, the frequency would vary by plus or minus 0.5 MHz in center-spread mode, or from 99 MHz to 100 MHz in down-spread mode. The relationship between spreading ratio, EMI reduction, and measurement bandwidth follows logarithmic principles: doubling the spreading ratio provides approximately 3 dB additional EMI reduction when measured with a fixed bandwidth receiver.
The actual EMI reduction achieved depends on the ratio between the spread bandwidth and the measurement receiver's resolution bandwidth. If the spread bandwidth significantly exceeds the resolution bandwidth, the reduction approaches the theoretical maximum of 10 log(spread bandwidth / resolution bandwidth). For typical CISPR measurements with 120 kHz resolution bandwidth, a 1% spread at 100 MHz creates a 2 MHz spread bandwidth, yielding approximately 12 dB reduction.
Modulation Frequency Selection
The rate at which the frequency sweeps through its range, called the modulation frequency, also affects EMI reduction and system behavior. Modulation frequencies typically range from 30 kHz to 60 kHz. Lower modulation frequencies improve EMI reduction by ensuring the frequency changes significantly during each measurement period, but may cause visible artifacts in display systems or audible noise in audio paths.
Higher modulation frequencies reduce these side effects but may not achieve optimal EMI reduction if the frequency changes too rapidly for the measurement receiver's time constants. The modulation frequency should also be chosen to avoid resonances with other system frequencies and to ensure adequate averaging within EMC measurement dwell times.
Center Spread vs. Down Spread
The choice between center spread and down spread configurations represents a fundamental design decision that affects timing margins, compatibility, and EMI reduction effectiveness. Each approach has distinct advantages depending on the application requirements.
Center Spread
Center spread modulation varies the frequency symmetrically around the nominal value, alternating between higher and lower frequencies. For a 100 MHz clock with 1% center spread, the frequency ranges from 99.5 MHz to 100.5 MHz. This approach maximizes the spread bandwidth for a given peak frequency deviation, providing optimal EMI reduction efficiency.
The symmetric variation means the average frequency equals the nominal frequency, which simplifies system timing analysis. However, the excursions to frequencies above the nominal value may violate maximum frequency specifications for some downstream components. Center spread is commonly used in systems where all components can tolerate the full frequency range and maximum EMI reduction is desired.
Down Spread
Down spread modulation keeps the maximum instantaneous frequency at or slightly below the nominal value, spreading the clock only to lower frequencies. For a 100 MHz clock with 1% down spread, the frequency ranges from 99 MHz to 100 MHz. This ensures that maximum frequency specifications are never violated, which is critical for systems with tight frequency constraints.
The asymmetric spreading means the average frequency is lower than the nominal value by half the spread amount. For the example above, the average frequency would be 99.5 MHz rather than 100 MHz. This shift must be accounted for in timing budgets. Down spread is the standard choice for computer systems, memory interfaces, and serial links where exceeding the nominal frequency could cause functional failures.
Impact on Timing Margins
Both spreading modes affect system timing margins, though in different ways. Center spread maintains the average frequency but introduces both faster and slower clock periods, affecting both setup and hold timing equally. Down spread only slows the clock, consuming setup margin while improving hold margin. The actual impact depends on whether timing is analyzed cycle-by-cycle or over longer periods.
For source-synchronous interfaces where data is captured relative to an accompanying clock, the impact of spreading is minimized because both signals experience the same frequency modulation. However, for mesochronous systems where local and remote clocks are nominally the same frequency but not phase-aligned, spreading can cause data eyes to wander within the bit period, requiring additional margin allocation.
Tracking Loops and Spread-Spectrum Recovery
When a spread-spectrum clock drives other PLLs in the system, those PLLs must either track the modulation or filter it out. The design choice between tracking and filtering depends on the downstream requirements and has significant implications for jitter performance and system compatibility.
Tracking Spread-Spectrum Input
A PLL can be designed to track the spread-spectrum modulation by ensuring its loop bandwidth is sufficiently high to follow the frequency variations. For a PLL to track a spread-spectrum input, its closed-loop bandwidth should be several times higher than the modulation frequency. This approach preserves the EMI reduction benefits throughout the clock tree while maintaining phase alignment between the input and output clocks.
Tracking PLLs must be carefully designed to prevent the modulation from exciting resonant behavior. If the loop bandwidth is close to the modulation frequency, the PLL's gain peaking can amplify the modulation, potentially worsening jitter rather than passing it through transparently. The loop dynamics must be analyzed considering the modulation as a deterministic input signal.
Filtering Spread-Spectrum Modulation
When downstream circuits require a clean, unmodulated clock, the receiving PLL can be configured with a low bandwidth that filters out the modulation. This approach is necessary when the spread-spectrum modulation would interfere with precision timing circuits, analog-to-digital converters, or other jitter-sensitive applications.
Filtering PLLs must have loop bandwidths significantly lower than the modulation frequency, typically at least an order of magnitude lower. The filtered PLL's output will have a constant frequency equal to the average input frequency, but the resulting phase difference between input and output will vary cyclically with the modulation. This growing and shrinking phase offset must be considered in system timing analysis.
Clock Data Recovery Considerations
Clock data recovery (CDR) circuits in serial communication receivers face particular challenges with spread-spectrum clocking. The CDR must track the incoming data's timing, which varies with the spread-spectrum modulation applied at the transmitter. If the CDR bandwidth is too low, it cannot follow the modulation, causing the sampling point to drift relative to the data eyes and increasing bit error rates.
High-speed serial standards like PCI Express and SATA include spread-spectrum clocking provisions and specify CDR bandwidth requirements that ensure proper tracking. Designers implementing custom protocols must carefully consider CDR bandwidth requirements when using spread-spectrum clocking to ensure reliable data recovery across the modulation range.
EMI Reduction Techniques and Measurements
Achieving optimal EMI reduction with spread-spectrum clocking requires understanding the measurement process and carefully selecting spreading parameters. The effectiveness of SSC depends on the relationship between spreading bandwidth, modulation rate, and measurement equipment characteristics.
Understanding EMC Measurements
EMC compliance testing uses spectrum analyzers or EMI receivers with standardized resolution bandwidths and detector types. CISPR 22/32 measurements for radiated and conducted emissions typically use quasi-peak detectors with specific resolution bandwidths: 9 kHz for frequencies below 150 kHz, 120 kHz for frequencies from 150 kHz to 30 MHz, and 120 kHz for frequencies above 30 MHz in conducted measurements, with 120 kHz used for radiated measurements up to 1 GHz.
The quasi-peak detector responds to both the amplitude and repetition rate of emissions. For spread-spectrum clocks, the frequency modulation causes the emission at any single frequency to be intermittent, reducing the quasi-peak reading compared to a continuous signal at the same peak amplitude. This provides additional EMI reduction beyond the pure power spreading effect.
Optimizing Spreading Parameters
Maximum EMI reduction occurs when the spreading bandwidth significantly exceeds the measurement resolution bandwidth and the modulation frequency is low enough that multiple modulation cycles occur within each measurement period. However, practical constraints often limit the spreading ratio due to timing margin requirements, and the modulation frequency may be constrained by audio or video artifacts.
Harmonics of the clock frequency experience proportionally larger absolute spreading, since a 1% spread at 100 MHz becomes 10 MHz at the tenth harmonic. This increased spreading provides greater EMI reduction at higher harmonics, which is beneficial because harmonics often dominate emissions in the hundreds of MHz to GHz range where radiated coupling is most efficient.
Measuring Spread-Spectrum Effectiveness
Verifying spread-spectrum clock operation and its EMI reduction effectiveness requires appropriate test equipment and techniques. A spectrum analyzer set to zero span mode at the fundamental or a harmonic frequency can visualize the modulation profile and verify the spreading bandwidth and modulation frequency. Comparing peak emissions with spread-spectrum enabled and disabled quantifies the actual EMI reduction achieved.
Care must be taken when measuring spread-spectrum clocks to ensure the measurement accurately represents what compliance testing will observe. Using the same detector types, resolution bandwidths, and dwell times as the compliance standards provides results that correlate well with actual EMC testing.
Implementation Considerations
Implementing spread-spectrum clocking involves both the SSC generator itself and careful consideration of its effects throughout the system. Proper implementation ensures EMI reduction is achieved without compromising functional performance.
SSC Generator Architectures
Spread-spectrum clocking can be implemented through various PLL architectures. Analog implementations modulate the VCO control voltage with a low-frequency signal, while digital implementations adjust the feedback divider ratio or directly control a digitally controlled oscillator. Fractional-N PLLs are particularly well-suited to SSC implementation because their inherent ability to synthesize fractional frequency ratios provides fine control over the instantaneous frequency.
The modulation path must be designed to avoid introducing additional jitter while allowing the frequency to track the modulation waveform accurately. Loop bandwidth and modulation rate must be coordinated so that the loop faithfully reproduces the intended modulation without overshoot, ringing, or excessive filtering that would reduce the effective spreading.
System Integration Challenges
Integrating spread-spectrum clocking into a complex system requires analysis of how the modulation affects each subsystem. Memory interfaces, high-speed serial links, display timing, and precision analog circuits may each have different sensitivities to the frequency modulation. A thorough timing analysis considering worst-case frequency deviations ensures reliable operation across the spread range.
Multiple clock domains present additional complexity. If different PLLs in the system handle the spread-spectrum modulation differently (some tracking, some filtering), phase relationships between domains will vary cyclically with the modulation. This can affect synchronizer metastability rates and data transfer timing between domains.
Standards and Specifications
Many industry standards include specific provisions for spread-spectrum clocking. PCI Express specifies down spread with -0.5% spreading ratio and 30-33 kHz modulation frequency. SATA allows both center spread and down spread with various ratios. USB, DisplayPort, and other standards have their own SSC specifications that ensure interoperability between devices from different manufacturers.
When designing systems intended for compliance with these standards, the specified SSC parameters must be implemented precisely. Both the spreading ratio and modulation frequency must fall within the allowed ranges, and the modulation profile must meet waveform requirements. Non-compliant SSC implementation can cause interoperability problems with other standard-compliant devices.
Summary
Spread-spectrum clocking provides an effective technique for reducing electromagnetic emissions without compromising signal integrity or adding physical shielding. By modulating the clock frequency according to carefully designed profiles and spreading ratios, peak emissions can be reduced by 6 to 20 dB, often making the difference between EMC compliance failure and success.
The choice between center spread and down spread depends on system requirements, with down spread being standard for applications where exceeding the nominal frequency is prohibited. Modulation profiles ranging from simple triangular waveforms to optimized Hershey-Kiss shapes offer trade-offs between implementation complexity and spectral flatness. Downstream PLLs must be designed to either track or filter the modulation depending on their application's jitter sensitivity.
Successful spread-spectrum implementation requires understanding both the EMC measurement process and the timing impact throughout the system. When properly designed and integrated, spread-spectrum clocking enables modern electronic systems to meet stringent EMC requirements while maintaining full functional performance, making it an essential technique in the digital designer's toolkit.