Electronics Guide

PWM Frequency Selection

The PWM switching frequency represents a fundamental design trade-off. Higher frequencies reduce current ripple and acoustic noise but increase switching losses in the power devices. Lower frequencies improve efficiency but may cause audible noise and require larger filter components to smooth the motor current.

Typical PWM frequencies range from 2 kHz for large industrial drives to 20 kHz or higher for servo applications and consumer products. The 20 kHz threshold is significant because it places the fundamental switching frequency above human hearing range, eliminating the characteristic whine associated with lower-frequency PWM.

The motor's electrical time constant, determined by its inductance-to-resistance ratio, establishes a lower bound on practical PWM frequency. The switching period should be significantly shorter than the electrical time constant to achieve smooth current with acceptable ripple. Conversely, the power device switching losses and thermal constraints establish upper bounds.

Duty Cycle and Voltage Control

The duty cycle, the fraction of each PWM period during which the high-side switch is on, directly determines the average voltage applied to the load. A 50% duty cycle produces an average voltage equal to half the DC bus voltage. Varying the duty cycle from 0% to 100% spans the full range of available average voltage.

In a half-bridge configuration driving one motor phase, the duty cycle maps directly to output voltage. In three-phase systems, the three duty cycles must be coordinated to produce the desired voltage vector while maintaining balanced operation and proper common-mode voltage.

Resolution of the duty cycle determines the granularity of voltage control. A PWM timer with 10-bit resolution provides 1024 discrete duty cycle levels, while 16-bit resolution enables over 65,000 levels. Higher resolution reduces quantization noise in the control loop and enables smoother operation at low speeds where voltage commands are small.

PWM Timer Architecture

Digital PWM generation typically uses hardware timer peripherals that compare a counter value against programmed thresholds. The counter increments (or decrements) with each clock cycle, and the output changes state when the counter matches the compare value. Different counter modes create different PWM waveform characteristics.

Modern microcontrollers designed for motor control include specialized PWM peripherals with features like automatic dead-time insertion, fault inputs for immediate shutdown, synchronized ADC triggering, and multiple independent channels for multi-phase applications. Understanding these hardware capabilities is essential for efficient implementation.

Operating Principle

In edge-aligned mode, each PWM period begins with the output in its active state. As the counter increments, it eventually reaches the compare value, at which point the output transitions to its inactive state. The output remains inactive until the counter resets and the next period begins.

The duty cycle is simply the ratio of the compare value to the counter's maximum value. A compare value of zero produces 0% duty cycle with the output always inactive, while a compare value equal to the maximum produces 100% duty cycle with the output always active.

The PWM frequency equals the timer clock frequency divided by the counter period (maximum count plus one). For example, a 100 MHz timer clock with a 16-bit counter produces PWM at approximately 1.5 kHz. Using a smaller counter period increases the PWM frequency at the cost of reduced duty cycle resolution.

Advantages and Applications

Edge-aligned PWM offers simplicity in both hardware and software implementation. A single counter direction and straightforward comparison logic minimize timer complexity. The well-defined timing of output transitions simplifies ADC synchronization when current sampling is required at specific points in the PWM cycle.

Single-phase applications like brushed DC motor control commonly use edge-aligned PWM. The asymmetric nature of the waveform is acceptable because only one voltage is being controlled. Simple half-bridge and full-bridge drivers for DC motors operate effectively with edge-aligned modulation.

Limitations

The primary limitation of edge-aligned PWM emerges in multi-phase applications. Because all phases align their switching transitions to the same edge, all high-side switches turn on simultaneously at the start of each PWM period. This synchronous switching creates large current spikes on the DC bus, increasing electromagnetic interference and ripple current stress on the bus capacitors.

Additionally, the asymmetric placement of pulses within the period produces higher harmonic content than symmetric alternatives. The fundamental component and its odd harmonics have larger amplitudes relative to the carrier frequency, potentially causing increased motor heating and acoustic noise.

For three-phase motor drives, edge-aligned PWM is generally inferior to center-aligned alternatives, though it may still find use in cost-sensitive applications where simplicity outweighs performance.

Operating Principle

In center-aligned mode, the PWM output activates when the up-counting counter reaches the compare value and deactivates when the down-counting counter again passes the compare value. This creates a pulse centered at the counter's peak, with equal durations on either side.

The effective PWM frequency is half what it would be for edge-aligned operation with the same counter period, because the counter must traverse its range twice (up and down) for each PWM cycle. Alternatively, the counter period can be halved to maintain the same PWM frequency.

The symmetry of the waveform about the period center produces beneficial spectral properties. The switching events are distributed more evenly in time, and the odd harmonics of the fundamental are naturally attenuated compared to edge-aligned modulation.

Benefits for Three-Phase Drives

Center-aligned PWM is strongly preferred for three-phase motor drives for several important reasons:

• Reduced DC bus ripple: The switching transitions of the three phases are naturally staggered in time rather than occurring simultaneously, distributing the current disturbance and reducing peak demands on bus capacitors.
• Lower EMI: Distributed switching events produce lower peak electromagnetic emissions compared to the concentrated switching of edge-aligned PWM.
• Improved current sampling: The symmetric structure creates a natural sampling point at the period center where the current equals its average value, simplifying control loop implementation.
• Better spectral content: The voltage spectrum has reduced harmonics near the carrier frequency and its odd multiples.

Implementation Considerations

Center-aligned operation requires timer peripherals that support up-down counting mode. Most modern motor control microcontrollers provide this capability, often with additional features specifically designed for center-aligned PWM generation.

Updating the compare values requires care to maintain symmetry. If a new compare value is loaded while the counter is in its up-count phase, it affects both the rising and falling edges of the current pulse. Some timers provide shadow registers that hold new values until a defined update point, ensuring consistent duty cycle changes.

ADC triggering typically occurs at the counter peak (where the voltage vector is at maximum magnitude) or at the counter zero (where the voltage vector may be at zero). The optimal sampling strategy depends on the control approach and the desired current measurement.

Comparison with Edge-Aligned PWM

Center-aligned PWM produces two switching transitions per phase per PWM period, compared to one for edge-aligned PWM at the same fundamental frequency. However, the reduced dv/dt stress and better spectral properties typically outweigh this disadvantage in three-phase applications.

The symmetric nature of center-aligned PWM also simplifies certain analytical calculations, as the average value of the switched waveform over any half-period equals the duty cycle times the bus voltage. This property is useful for both control design and current sensing.

Voltage Vector Concept

A three-phase voltage source inverter has eight possible switching states, determined by the combination of the three upper switches being on or off. Two of these states are zero vectors where all upper switches are either on or off, producing zero output voltage. The remaining six states produce non-zero voltage vectors arranged uniformly in a hexagonal pattern.

The six active vectors divide the voltage plane into six sectors, each spanning 60 degrees. Any desired voltage vector within the hexagon can be synthesized by applying the two adjacent active vectors and the zero vectors for appropriate durations within the PWM period. The time spent in each state determines the magnitude and angle of the average voltage vector.

The maximum voltage vector magnitude that can be continuously produced is the radius of the largest circle inscribed within the hexagon. This represents approximately 15% higher DC bus utilization compared to sinusoidal PWM, enabling more voltage output for the same bus voltage or lower bus voltage for the same output requirement.

SVM Algorithm Implementation

Implementing SVM requires several computational steps performed each PWM period:

Sector identification: Determine which of the six sectors contains the desired voltage vector. This is typically accomplished by examining the signs and relative magnitudes of the alpha-beta components of the voltage command.

Dwell time calculation: Calculate the time durations for the two adjacent active vectors and the zero vectors. The durations depend on the vector magnitude, angle within the sector, and PWM period. Standard formulas express these times in terms of the reference voltage components.

Switching sequence generation: Arrange the calculated dwell times into a switching sequence that minimizes transitions and centers the active vectors within the period. The typical seven-segment sequence applies vectors in order 0-1-2-7-2-1-0, where 0 and 7 are zero vectors and 1 and 2 are the adjacent active vectors.

Timer value computation: Convert the dwell times to compare values for the PWM timer registers. This step maps the abstract SVM calculation to the specific timer hardware being used.

Advantages of Space Vector Modulation

SVM offers several significant advantages over carrier-based PWM approaches:

• Higher DC bus utilization: The approximately 15% improvement in maximum voltage enables higher motor speeds or lower bus voltage requirements.
• Flexible zero vector selection: The algorithm can choose between zero vectors to optimize for different criteria such as minimum switching losses or reduced common-mode voltage.
• Natural center alignment: The symmetric switching sequence inherently produces center-aligned waveforms with their associated benefits.
• Direct voltage vector control: The voltage vector is specified directly, simplifying integration with vector control algorithms that naturally produce voltage commands in the alpha-beta reference frame.
• Reduced harmonic distortion: Properly implemented SVM produces lower total harmonic distortion than sinusoidal PWM.

Variations and Extensions

Several variations of basic SVM address specific requirements:

Discontinuous PWM (DPWM): By modifying the zero vector allocation, one phase can be held constant (clamped to the positive or negative rail) during part of each fundamental cycle. This reduces switching losses by eliminating one-third of the transitions at the cost of slightly higher harmonic content.

Reduced common-mode voltage SVM: Selecting zero vectors to minimize the common-mode voltage reduces bearing currents and EMI in motor drives. This technique avoids using the 000 and 111 states when possible.

Overmodulation: When the requested voltage vector exceeds the linear modulation range, overmodulation techniques extend output capability at the cost of increased harmonics. This is useful for maximizing motor output near the voltage limit.

The Need for Dead Time

Power semiconductor switches do not turn on and off instantaneously. When commanded off, a switch continues conducting for a brief period while stored charge is removed and the device transitions to its blocking state. If the complementary switch were turned on immediately, both devices would conduct simultaneously until the turning-off device completed its transition.

Simultaneous conduction creates a low-impedance path directly across the DC bus. The resulting shoot-through current is limited only by the device on-state resistances and parasitic inductances. This current can reach destructive levels in microseconds, damaging or destroying the power devices and potentially causing catastrophic inverter failure.

Dead time provides a safety margin during which neither switch in a half-bridge leg is commanded on. The turning-off device has time to fully block before the turning-on device begins conducting. This margin must accommodate the worst-case turn-off time plus appropriate safety factors.

Dead-Time Duration Selection

The dead-time duration must exceed the turn-off time of the power devices under worst-case conditions. Factors affecting the required dead time include:

• Device technology: IGBTs typically require longer dead times than MOSFETs due to their minority carrier storage time.
• Temperature: Switching times generally increase at higher temperatures, requiring longer dead time for hot operating conditions.
• Gate drive strength: Weaker gate drive results in slower switching and requires longer dead time.
• Load current: Turn-off time may vary with the current being switched.
• Safety margin: Additional margin accounts for component variation and unexpected conditions.

Typical dead-time values range from 100 nanoseconds for fast MOSFETs to several microseconds for large IGBTs. The exact value should be verified through testing across the full operating range.

Dead-Time Effects on Output Voltage

Dead time introduces distortion in the output voltage waveform. During the dead-time interval, the output is not directly controlled by the PWM command but rather depends on the load current direction. If current is flowing out of the phase, the antiparallel diode of the lower switch conducts, pulling the output low. If current is flowing into the phase, the upper diode conducts, pulling the output high.

This current-dependent behavior creates a voltage error that appears as low-frequency distortion in the motor current. The distortion is most significant at low output voltages and low speeds, where the dead-time intervals represent a larger fraction of the total PWM period. The effect is a reduction in average output voltage in the direction opposite to current flow.

Dead-time compensation algorithms attempt to correct this distortion by adjusting the PWM duty cycles based on measured or estimated current direction. However, perfect compensation is difficult because the current direction may change during the PWM period, particularly at current zero crossings.

Hardware Dead-Time Implementation

Most motor control microcontrollers include hardware support for automatic dead-time insertion. The PWM peripheral generates complementary outputs for upper and lower switches, automatically inserting the configured dead time at each transition. This hardware approach ensures consistent dead time regardless of software timing variations.

Programmable dead time allows adjustment for different power device technologies or operating conditions. Some designs implement adaptive dead time that varies based on current level or temperature, optimizing efficiency while maintaining safe operation.

Independent rising and falling edge dead times can compensate for asymmetric device switching characteristics. If the turn-on time differs significantly from the turn-off time, different dead times on each edge can minimize total distortion while maintaining protection.

Hardware Interlock Circuits

Hardware interlock circuits in the gate driver prevent simultaneous turn-on of complementary switches regardless of the control signals received. Even if the controller erroneously commands both switches on, the interlock ensures only one can conduct.

Gate driver ICs with integrated interlock typically implement this through logic that ignores the turn-on command for one switch until the other has been off for a minimum time. This hardware-level protection operates independently of the microcontroller and cannot be overridden by software bugs or control signal glitches.

Some interlock designs include programmable delay elements that allow customization of the protection timing. Others provide fixed delays chosen to accommodate common device types. The protection threshold should exceed the worst-case device switching times with appropriate margin.

Desaturation Detection

Desaturation detection monitors the collector-emitter or drain-source voltage of the power switch during conduction. Under normal operation, this voltage is low (the saturation voltage). If a shoot-through or other overcurrent condition occurs, the increased current drives the device out of saturation, causing the conduction voltage to rise.

The detection circuit compares the device voltage against a threshold after blanking time allows for normal turn-on transients. If the voltage exceeds the threshold, indicating desaturation, the gate driver immediately turns off the device and signals a fault condition. This response occurs in hundreds of nanoseconds, much faster than software protection could react.

Desaturation protection is particularly important for IGBTs, which can be damaged by short-circuit conditions in microseconds. The fast response of desaturation detection limits the energy delivered during a fault, potentially preventing device destruction.

DC Bus Current Monitoring

Monitoring the DC bus current provides another layer of shoot-through detection. During normal operation, the bus current follows predictable patterns related to the PWM switching and motor current. A sudden spike in bus current indicates a potential shoot-through or other fault condition.

Hardware comparators can trigger fault responses when bus current exceeds a threshold. The response may shut down all PWM outputs, engage braking resistors, or take other protective actions. The threshold must be set above normal transient peaks but below levels that would damage components.

Some designs use both fast analog detection and software monitoring. The hardware comparator provides immediate protection against severe faults, while software monitors detect developing problems and can provide diagnostic information about fault conditions.

Fault Response and Recovery

When shoot-through protection detects a fault, the response must be immediate and fail-safe. All PWM outputs should transition to a safe state, typically with all switches off or with a controlled braking configuration. The response must occur without depending on software execution, ensuring protection even if the processor has malfunctioned.

After a fault, recovery procedures should verify system integrity before resuming normal operation. This may include checking for damaged components, verifying control signal integrity, and performing diagnostic tests. Automatic recovery from transient faults may be appropriate in some applications, while others require manual intervention and investigation.

Fault logging and diagnostics help identify the root cause of shoot-through events. Recording the conditions leading to the fault, including duty cycles, currents, and temperatures, aids troubleshooting and can reveal systematic issues requiring design changes.

Current Sensing Methods

Accurate current measurement is the foundation of current limiting. Several sensing technologies serve motor drive applications:

Shunt resistors: Low-value precision resistors in the current path produce voltage proportional to current. Phase-leg shunts measure individual phase currents, while DC bus shunts measure the total bus current. Shunt sensing offers high bandwidth and low cost but dissipates power and requires attention to thermal management and isolation.

Hall effect sensors: These devices measure the magnetic field produced by current flow without inserting resistance in the power path. Hall sensors provide galvanic isolation and can measure high currents without significant power dissipation. However, they have limited bandwidth and are susceptible to magnetic interference.

Current transformers: Used primarily for AC current measurement, current transformers provide isolated sensing with good bandwidth. They work well for phase current measurement in AC motor drives but cannot measure DC components.

Integrated current sensing: Some power modules include built-in current sensors, simplifying the drive design. These may use any of the above technologies, integrated during module manufacturing for optimal placement and calibration.

Hardware Current Limiting

Hardware current limiting provides the fastest response to overcurrent conditions, essential for protecting devices with limited short-circuit withstand capability. Analog comparators monitor the current sense signal and trip when a threshold is exceeded.

The PWM peripheral can include hardware trip inputs that immediately force outputs to a safe state when triggered by the current comparator. This response occurs within nanoseconds, independent of software execution. The hardware may latch the fault condition, requiring explicit clearing before resuming operation.

Cycle-by-cycle current limiting adjusts PWM on-time within each switching period to prevent current from exceeding the limit. When current reaches the threshold, the PWM pulse terminates early regardless of the commanded duty cycle. This technique provides tight current control at the cost of increased ripple when operating at the current limit.

Software Current Limiting

Software current limiting operates within the control loop, adjusting current or torque commands to keep actual current within safe bounds. The control algorithm monitors measured current and reduces commands when approaching limits.

Anti-windup strategies prevent the current controller from commanding excessive voltage when current is limited. Without anti-windup, the integrator in a PI controller continues accumulating error during current limiting, causing overshoot when the limit condition ends. Proper anti-windup maintains integrator values at levels appropriate for the limited current condition.

Software limiting can implement sophisticated strategies such as I2t protection, which limits the accumulated energy (integral of current squared over time) rather than instantaneous current. This allows brief current peaks for transient events while preventing thermal damage from sustained overcurrent.

Coordinated Protection Strategy

Effective current protection combines multiple layers operating at different time scales:

• Hardware instantaneous protection: Responds in nanoseconds to protect against shoot-through and severe faults. Threshold set well above normal operating peaks.
• Cycle-by-cycle limiting: Operates within each PWM period to prevent current runaway. Threshold set at the maximum safe device current.
• Software peak limiting: Updates each control cycle to limit current command. Threshold set at the continuous operating limit.
• Thermal protection: Monitors temperature and derated current capability. Reduces limits when temperature rises to prevent thermal runaway.
• I2t protection: Tracks cumulative thermal stress and limits operation accordingly. Allows short-term overloads within safe bounds.

Random PWM and Spread Spectrum

Conventional fixed-frequency PWM concentrates electromagnetic emissions at the switching frequency and its harmonics. Random PWM intentionally varies the switching frequency within a defined range, spreading the emission energy across a broader spectrum and reducing peak levels.

Spread spectrum techniques can dramatically reduce EMI compliance challenges by lowering the peaks that regulatory limits specify. The motor inductance averages the randomized switching, so motor performance is largely unaffected. The primary trade-off is increased difficulty in synchronizing ADC sampling and potential interaction with resonances in the mechanical system.

Multi-Level PWM

Multi-level inverters use additional switches to create intermediate voltage levels between the positive and negative rails. Three-level designs add a neutral point connection, while more complex topologies provide additional levels. Each additional level reduces the voltage step size and thus the harmonic content of the output.

PWM generation for multi-level inverters extends the concepts of two-level modulation. Space vector approaches define additional voltage vectors corresponding to the intermediate states. Carrier-based methods use multiple interleaved carriers to generate the multi-level output. The added complexity provides benefits in high-power applications where reduced harmonics and lower device stress justify the additional components.

Interleaved PWM

Interleaving uses multiple parallel converter legs with phase-shifted PWM carriers to reduce ripple current. When two half-bridges operate 180 degrees out of phase, their ripple currents partially cancel in the output and input. More phases with appropriate phase shifts can further reduce ripple.

Interleaving is particularly beneficial for DC-DC converters and motor drives where ripple current causes losses and requires large filter components. The reduced ripple allows smaller capacitors and inductors, potentially offsetting the cost of additional switching components.

PWM Timer Configuration

Proper timer configuration is essential for reliable PWM generation. Key considerations include:

• Clock source selection: Use the highest-frequency stable clock available to maximize duty cycle resolution.
• Counter period calculation: Select the period to achieve the desired PWM frequency while maintaining adequate resolution.
• Compare value scaling: Map control algorithm output to compare values using fixed-point arithmetic to avoid floating-point overhead.
• Update synchronization: Load new compare values at appropriate points to avoid glitches or asymmetric pulses.
• ADC trigger timing: Configure triggers to sample current at optimal points relative to switching events.

Fault Handling Architecture

A robust fault handling architecture ensures safe response to all anticipated failure modes:

Design the hardware fault path to operate independently of software. Hardware comparators and logic should force safe states without CPU intervention. Software cannot be relied upon during processor crashes or lockups.

Implement fault prioritization for multiple simultaneous faults. Some conditions require immediate shutdown while others allow controlled stops. The response should match the severity and urgency of each fault type.

Provide comprehensive fault diagnostics. Log fault conditions, timing, and context to support root cause analysis. Distinguish between different fault types to guide troubleshooting.

Testing and Validation

Thorough testing validates PWM generation under all operating conditions:

• Duty cycle range: Verify correct operation at minimum, maximum, and intermediate duty cycles.
• Dead-time verification: Confirm dead time at all operating points and temperatures using high-speed measurements.
• Fault injection: Test response to simulated faults including overcurrent, desaturation, and control signal errors.
• Thermal stress: Verify current limiting and protection under thermal stress conditions.
• EMI compliance: Measure electromagnetic emissions to verify regulatory compliance.