Electronics Guide

Understanding the Technologies

ASICs are custom-designed integrated circuits optimized for a specific application. The design is committed to silicon through a fabrication process that creates permanent circuit structures. Once manufactured, an ASIC cannot be modified; any design changes require a new fabrication run with associated costs and delays.

FPGAs contain arrays of configurable logic blocks connected through programmable interconnects. The functionality is defined by loading a configuration bitstream into the device, which can be changed at any time. This programmability provides flexibility but comes with overhead in terms of area, power, and performance compared to equivalent ASIC implementations.

Structured ASICs and similar technologies occupy a middle ground, offering some customization with reduced non-recurring engineering costs compared to full-custom ASICs. These options can provide attractive trade-offs for medium-volume applications where pure ASIC economics are marginal but FPGA limitations are problematic.

Cost Structure Comparison

The economic comparison between ASIC and FPGA involves analyzing both non-recurring engineering (NRE) costs and per-unit production costs:

ASIC Cost Structure:

• NRE costs: Typically range from hundreds of thousands to millions of dollars, including design, verification, mask sets, and initial production setup
• Unit costs: Generally lower than equivalent FPGAs, especially at advanced nodes and high volumes
• Mask costs: Can exceed several million dollars at leading-edge nodes (7nm and below)
• Design tools: Expensive EDA licenses required, though often already available in organizations doing ASIC work

FPGA Cost Structure:

• NRE costs: Minimal beyond design tool licenses and engineering time
• Unit costs: Higher than equivalent ASIC functionality, with prices ranging from a few dollars to thousands depending on capacity
• Development hardware: Evaluation boards and development kits available at modest cost
• Design tools: Vendor tools often free or low-cost for basic functionality

The crossover volume where ASIC becomes more economical depends on the specific implementation but typically ranges from tens of thousands to hundreds of thousands of units. Below this volume, the high ASIC NRE cannot be amortized sufficiently, making FPGA more economical despite higher unit costs.

Performance and Power Trade-offs

ASICs typically achieve 3-10x better performance and power efficiency compared to FPGA implementations of equivalent functionality. This advantage stems from several factors:

Logic density: ASIC standard cells implement functions more efficiently than FPGA lookup tables, requiring less silicon area for equivalent logic.

Routing efficiency: ASIC metal routing is optimized for the specific design, while FPGA programmable interconnects add parasitic capacitance and resistance.

Clock distribution: ASICs can implement optimized clock trees, while FPGAs must use generic clock resources that may not perfectly match design requirements.

Power optimization: ASICs can use multiple threshold voltage libraries and fine-grained power gating, optimizations difficult or impossible in FPGAs.

For applications where performance or power efficiency is paramount, such as high-volume consumer devices or data center accelerators, these advantages often justify ASIC development despite higher NRE costs.

Time to Market Considerations

FPGA development cycles are typically much shorter than ASIC cycles:

FPGA development: Design, implementation, and testing can often be completed in weeks to months, with immediate ability to program and test hardware.

ASIC development: Full-custom ASIC development typically requires 12-24 months from specification to production silicon, with significant delays for mask fabrication and first silicon bring-up.

In markets where timing is critical, the ability to reach market quickly with an FPGA solution may outweigh the unit cost advantages of an ASIC. Products can establish market presence and generate revenue while an ASIC version is developed in parallel for later cost reduction.

FPGAs also provide flexibility to respond to changing requirements or standards. Design modifications can be implemented through bitstream updates without hardware changes, valuable when specifications are evolving or customer requirements are not fully defined.

Risk Assessment

Each technology path carries different risk profiles that must be evaluated:

ASIC risks:

• Design bugs may require expensive mask respins
• Changing requirements after tape-out are costly to address
• Long development cycles increase market uncertainty
• High NRE investment may be lost if product fails commercially

FPGA risks:

• Higher unit costs may make products uncompetitive at scale
• Performance limitations may prevent meeting requirements
• Vendor dependency on FPGA supplier for availability and roadmap
• Design security concerns with programmable devices

Organizations often mitigate risks by beginning development on FPGA platforms, validating functionality and market fit before committing to ASIC development. This approach combines FPGA flexibility with ASIC economics for production volumes.

Strategic Considerations

Core competencies and competitive differentiation heavily influence make versus buy decisions:

Core technology: Functions that provide competitive advantage typically warrant internal development to maintain control and build expertise. Companies derive value from capabilities their competitors cannot easily replicate.

Commodity functions: Standard functions available from multiple sources with little differentiation potential are often better acquired externally, freeing internal resources for higher-value activities.

Strategic importance: Even non-differentiating functions may merit internal development if they are critical to product roadmaps or if external supply uncertainty poses unacceptable risks.

The boundaries between core and commodity shift over time as technologies mature. What was once a differentiating capability may become widely available, while new technologies create opportunities for differentiation.

Economic Analysis

Thorough economic analysis compares total costs of internal development against external acquisition:

Internal development costs:

• Engineering salaries and overhead
• Design tools and infrastructure
• Development time opportunity cost
• Ongoing maintenance and enhancement
• Risk of schedule delays or technical failures

External acquisition costs:

• License fees (one-time and recurring)
• Per-unit royalties where applicable
• Integration engineering effort
• Vendor support and maintenance fees
• Switching costs if changing vendors later

Economic comparison must account for the full lifecycle, not just initial costs. Ongoing maintenance, future enhancements, and long-term vendor relationships all factor into the total cost of ownership.

Technical Evaluation

Technical capabilities must support project requirements regardless of source:

For internal development: Does the organization have the necessary expertise, tools, and capacity? Can the technology be developed within schedule and budget constraints? Are there unacceptable technical risks?

For external acquisition: Does the available solution meet technical requirements? Can it be integrated effectively with other system components? Is the vendor technically capable of supporting the product long-term?

Sometimes the right choice is hybrid approaches: acquiring base technology and customizing or extending it internally. This approach can combine external expertise with internal differentiation while managing development risk.

Intellectual Property Considerations

IP rights significantly impact make versus buy economics and strategy:

License terms: Understanding exactly what rights are granted, including field of use restrictions, sublicensing rights, and derivative work provisions.

Patent exposure: External IP may come with indemnification, while internal development requires freedom-to-operate analysis to avoid infringement.

Trade secrets: Internal development maintains confidentiality, while external acquisition may require revealing strategic information to vendors.

Exit provisions: What happens if the vendor relationship ends? Are there escrow arrangements for source code or design files?

Node Characteristics

Different process nodes offer varying capabilities:

Mature nodes (65nm and above):

• Lower mask costs and well-characterized processes
• Multiple foundry sources providing supply security
• Adequate for many applications without demanding performance requirements
• Lower design complexity with relaxed design rules

Mainstream nodes (28nm-14nm):

• Good balance of performance, power, and cost
• Broad IP availability and design ecosystem
• Suitable for medium-complexity digital designs
• Established yield and reliability data

Advanced nodes (7nm and below):

• Highest performance and transistor density
• Extreme mask costs (potentially exceeding $100 million for full mask set)
• Limited foundry sources
• Complex design rules requiring advanced EDA tools

Selection Criteria

Technology node selection should be driven by application requirements:

Performance requirements: Do speed or computational demands necessitate leading-edge nodes, or can requirements be met with older technology?

Power constraints: Battery-powered or thermally constrained applications may benefit from advanced nodes with lower dynamic and static power.

Die size and cost: Larger designs benefit more from density improvements; smaller designs may not justify the higher wafer costs of advanced nodes.

Volume projections: High volumes can amortize NRE over more units, potentially justifying more aggressive node selection.

Time to market: Established nodes offer faster development cycles with better tool support and more available IP.

Economic Trade-offs

Node economics involve complex trade-offs:

Advanced nodes reduce die area for a given function, potentially lowering the number of die per wafer cost. However, wafer costs increase significantly at each node due to process complexity, additional mask layers, and lower yields.

The net unit cost depends on how these factors balance for a specific design. Large, compute-intensive designs benefit most from area reduction at advanced nodes. Smaller designs or those with significant analog content may achieve lower costs at mature nodes.

Design costs also increase at advanced nodes due to more complex design rules, longer verification cycles, and more sophisticated manufacturing requirements. These increased NRE costs must be amortized over production volume.

Future-Proofing Considerations

Technology node decisions should account for the full product lifecycle:

Long-term availability: Mature nodes typically remain available longer, important for products with extended lifecycles such as industrial or automotive applications.

Performance headroom: Selecting a node with margin above current requirements provides room for feature growth without requiring process migration.

Second-source options: Older nodes often have multiple foundry sources, reducing supply chain risk.

Migration paths: Understanding potential future migrations helps inform design decisions that minimize porting effort if node changes become necessary.

Package Types

Common package technologies offer different trade-offs:

Wire bond packages: Traditional technology using gold or copper wires to connect die pads to package leads. Mature, cost-effective, and available in many form factors from small QFN packages to large BGAs.

Flip-chip packages: Die is inverted and connected through solder bumps directly to the package substrate. Provides shorter interconnects, lower inductance, and higher I/O density than wire bonding.

Chip-scale packages (CSP): Package footprint approaches die size, minimizing board area. Suitable for space-constrained applications but may limit I/O count and thermal dissipation.

Multi-chip modules (MCM): Multiple die assembled in a single package, enabling heterogeneous integration and reduced system footprint. Higher cost but can provide system-level benefits.

System-in-package (SiP): Advanced packaging integrating multiple die, passive components, and potentially other elements in a single package. Enables complete subsystem integration.

Electrical Considerations

Package electrical characteristics affect signal integrity and power delivery:

Inductance: Package lead and bond wire inductance limits high-frequency performance and causes power supply noise. Flip-chip packages generally provide lower inductance than wire bond alternatives.

Capacitance: Inter-lead capacitance and package parasitics affect signal timing and crosstalk. High-speed designs require careful package modeling.

Power delivery: Adequate power and ground connections are essential for supply integrity. Large digital designs may require hundreds of power supply pins.

Signal routing: Complex packages may include multiple metal layers for signal routing, enabling sophisticated pin assignment and impedance-controlled traces.

Thermal Management

Package thermal performance determines how effectively heat can be removed from the die:

Thermal resistance: Junction-to-ambient and junction-to-case thermal resistances determine die temperature for a given power dissipation and ambient conditions.

Heat spreading: Exposed die pads, thermal vias, and heat spreaders improve thermal conduction from the die to the board or heatsink.

Heatsink attachment: Some packages support direct heatsink attachment through exposed lids or integrated heat spreaders, enabling higher power dissipation.

Thermal interface: The connection between package and heatsink or board significantly affects overall thermal resistance. Material selection and assembly quality are critical.

Mechanical and Reliability Factors

Package mechanical properties affect reliability and manufacturing:

CTE matching: Coefficient of thermal expansion mismatches between die, package, and board create stress during temperature cycling, potentially causing solder joint or die attach failures.

Moisture sensitivity: Some packages absorb moisture that can cause damage during reflow soldering. Moisture sensitivity level ratings guide handling and storage requirements.

Mechanical protection: Package encapsulation protects the die from physical damage, contamination, and environmental exposure.

Board-level reliability: Drop test, vibration, and thermal cycling performance depend on package construction and solder joint configuration.

Cost Analysis

Package costs vary widely based on technology and complexity:

Package material cost: Substrate material, lead frame, mold compound, and other materials contribute to base package cost.

Assembly cost: Die attach, wire bonding or flip-chip bumping, encapsulation, and test add processing costs.

Yield considerations: Complex packages with high I/O counts have higher defect rates, affecting effective cost.

Test access: Package design affects testability; some configurations require specialized test equipment or longer test times.

Simple QFN or small BGA packages may cost tens of cents, while advanced multi-chip packages can cost tens of dollars. Package cost should be evaluated in the context of total system cost and value delivered.

Commercial EDA Tools

Leading commercial EDA vendors provide comprehensive tool suites:

Advantages:

• Comprehensive functionality covering the full design flow
• Extensive verification capabilities essential for complex designs
• Strong foundry support with certified design kits
• Professional support and regular updates
• Established interoperability and industry-standard formats

Disadvantages:

• High license costs, often hundreds of thousands of dollars annually
• Complex license management requirements
• Vendor lock-in through proprietary formats and flows
• Steep learning curves for advanced features

FPGA Vendor Tools

FPGA vendors provide tools optimized for their devices:

Advantages:

• Optimal support for vendor-specific device features
• Free or low-cost basic versions available
• Integrated development environments simplifying design flow
• Direct path from design to device programming

Disadvantages:

• Limited to specific vendor's devices
• May lack advanced features of third-party tools
• Design portability challenges when changing FPGA vendors
• Premium features may require paid licenses

Open-Source Options

Open-source EDA tools have matured significantly:

Advantages:

• No license costs
• Source code access enables customization
• Community support and continuous improvement
• Educational value from understanding tool internals

Disadvantages:

• May lack advanced features of commercial tools
• Limited foundry support and PDK availability
• Support through community forums rather than vendor contracts
• Integration challenges between tools from different sources

Open-source tools are increasingly viable for educational use, prototyping, and some production applications, though complex ASIC designs typically still require commercial tools.

Tool Evaluation Criteria

Systematic tool evaluation should consider:

Capability fit: Does the tool support required design methodologies, target technologies, and design complexity?

Interoperability: How well does the tool integrate with existing flows, other tools, and industry-standard formats?

Usability: What is the learning curve, and how does the tool affect designer productivity?

Support: What level of vendor support is available, and what is the user community like?

Cost: What are the total costs including licenses, maintenance, training, and infrastructure?

Roadmap: Does the vendor's development direction align with organizational needs?

Technical Capability Assessment

Evaluate vendor technical competencies:

Product specifications: Do vendor offerings meet current and anticipated technical requirements? Is there margin for future requirements?

Quality systems: What quality certifications does the vendor maintain? How do they handle quality issues and continuous improvement?

Technical support: What engineering support is available during design and production? How responsive is the support organization?

Documentation: Is product documentation complete, accurate, and well-maintained?

Reference designs: Does the vendor provide reference designs or application notes that accelerate development?

Business Viability

Assess vendor business stability and commitment:

Financial health: Review financial statements, credit ratings, and market position to assess stability.

Market presence: Is the vendor a leader in their segment, or a niche player? What is their competitive position?

Investment: Does the vendor invest in R&D and demonstrate technology leadership?

Customer base: Does the vendor serve similar customers and applications? Are there reference customers?

Longevity commitment: What is the vendor's policy on product lifecycle support and obsolescence?

Supply Chain Considerations

Evaluate supply chain reliability and flexibility:

Manufacturing locations: Where are products manufactured? What geographic or political risks exist?

Capacity: Can the vendor scale to meet volume requirements, including unexpected demand increases?

Lead times: What are typical and extended lead times? How does the vendor perform against commitments?

Inventory policies: Does the vendor maintain safety stock? What are terms for demand forecasting and commitment?

Second sources: Are alternative sources available for critical components?

Commercial Terms

Negotiate favorable commercial arrangements:

Pricing: What pricing is offered at various volumes? Are there opportunities for cost reduction over time?

Payment terms: What payment terms are standard, and what flexibility exists?

Warranties: What warranties are provided, and what is the claims process?

Liability: What liability does the vendor accept for product defects or delivery failures?

Intellectual property: What IP rights are granted with product purchase? Are there restrictions on use?

Relationship Development

Build strategic vendor relationships:

Communication: Establish regular communication channels for technical and commercial matters.

Roadmap alignment: Share product roadmaps to ensure vendor offerings continue to meet evolving requirements.

Early engagement: Involve key vendors early in new product development to leverage their expertise and ensure component availability.

Issue resolution: Establish clear processes for resolving problems when they inevitably arise.

Performance feedback: Provide regular feedback on vendor performance, both positive and constructive.

Requirements Definition

Begin with clear requirements:

• Technical requirements: Performance, power, size, interfaces, environmental conditions
• Economic requirements: Target unit cost, development budget, volume projections
• Schedule requirements: Time to market, development milestones, product lifecycle
• Strategic requirements: Differentiation needs, IP considerations, organizational capabilities

Requirements should be prioritized and weighted to guide trade-off decisions when perfect solutions do not exist.

Option Generation

Identify feasible technology options:

Consider multiple implementation approaches including different architectures, technology combinations, and sourcing strategies. Avoid premature convergence on a single option before alternatives have been explored.

Engage cross-functional input from engineering, manufacturing, supply chain, and business teams to ensure all relevant options are considered.

Evaluation and Comparison

Systematically evaluate options against requirements:

Develop evaluation criteria aligned with requirements and assign weights reflecting relative importance. Score each option against criteria, documenting rationale for scores.

Conduct sensitivity analysis to understand how conclusions change if assumptions or weights vary. Identify which factors most strongly influence the outcome.

Risk Assessment

Evaluate risks associated with each option:

Identify technical risks (can we make it work?), schedule risks (can we deliver on time?), cost risks (will costs meet projections?), and supply risks (will components be available?). Assess both probability and impact of risks, and identify mitigation strategies.

Consider how risks combine across the project. Multiple moderate risks may create unacceptable cumulative exposure even if each individual risk seems manageable.

Decision and Documentation

Make and document the decision:

Select the option that best satisfies weighted requirements while presenting acceptable risk. Document the decision rationale, including rejected alternatives and the reasons they were not selected.

Identify key assumptions underlying the decision and establish checkpoints to validate those assumptions as the project progresses. Be prepared to revisit the decision if assumptions prove incorrect.