Digital Communication Physical Layer

The physical layer forms the foundation of every digital communication system, defining how raw bits are converted into electrical, optical, or electromagnetic signals for transmission across physical media. As the lowest layer of the OSI reference model, it specifies signaling levels, timing, connectors, and the modulation and coding that together determine data rates, transmission distance, noise immunity, and overall link reliability. A solid grasp of physical layer concepts is essential for designing systems that move data dependably between devices, whether across a printed-circuit-board trace, a backplane, a copper cable, or an optical fiber.

Physical layer techniques have evolved dramatically, from the simple on-off signaling of early digital systems to the multi-level modulation used in modern high-speed links. Contemporary serial interfaces transmit four-level pulse-amplitude modulation (PAM4) at 112 gigabaud to reach 224 gigabits per second on a single differential lane, and aggregate many such lanes into the terabit-class links that bind processors, accelerators, and memory in current platforms. Achieving these rates demands disciplined attention to signal integrity, because every doubling of speed sharpens the effects of channel loss, reflection, crosstalk, and jitter.

The sections below break the physical layer into its principal building blocks. Line coding shapes the transmitted symbol stream so that a receiver can recover both data and clock while keeping the signal spectrum well behaved. Channel coding adds controlled redundancy so that errors introduced by the medium can be detected and corrected. Equalization techniques reverse the frequency-dependent distortion a real channel imposes, reopening the eye diagram at the receiver. Serializer-deserializer (SerDes) design ties these ideas together in the transceiver hardware that converts between slow parallel buses and fast serial links. Beneath all of these techniques, information theory establishes the ultimate limit: the maximum rate at which a given channel can carry data reliably, the benchmark against which every practical design is measured.

Articles in This Category

Channel Coding - Adding structured redundancy so a receiver can detect and correct the errors a channel introduces, covering block and convolutional codes, the capacity-approaching turbo, LDPC, and polar codes, and the interleaving and puncturing that adapt them to real links.
Equalization Techniques - Compensating for the frequency-dependent loss of a real channel with transmit pre-emphasis, continuous-time linear equalizers, feed-forward and decision-feedback equalizers, and the adaptive algorithms that tune them to reopen the receiver eye.
Information Theory and Channel Capacity - Establishing the fundamental limits on reliable communication through entropy, mutual information, and the Shannon-Hartley capacity theorem, including the bounds imposed by additive-white-Gaussian-noise and fading channels.
Line Coding - Mapping bits onto the transmitted symbol stream to control the signal spectrum, guarantee enough transitions for clock recovery, and bound the running disparity, spanning NRZ, Manchester, 8B/10B, 64B/66B, and multilevel PAM-4 signaling.
Serializer-Deserializer Design - Building the transceiver hardware that bridges slow parallel buses and fast serial lanes, covering parallel-to-serial conversion, clock multiplication, clock and data recovery, word alignment, and comma detection.

Signals, Symbols, and the Transmission Medium

At the physical layer, information exists as physical quantities that vary over time: voltage, current, light intensity, or radio field strength. A line code first maps groups of bits onto discrete signal levels called symbols, and a driver launches those symbols onto the medium. High-speed electrical links almost always use differential signaling, in which each bit travels as the difference between two complementary conductors. This scheme rejects common-mode noise and confines the return current, which is why standards such as PCI Express, USB, Serial ATA, and Ethernet all rely on it.

The medium itself governs what is achievable. A short trace between two chips on a printed circuit board behaves very differently from a meter of twinaxial copper cable, a backplane that spans several connectors, or a kilometer of optical fiber. Copper channels attenuate high frequencies far more than low ones, so a fast edge arrives at the receiver rounded and spread in time; optical fiber offers enormous bandwidth but adds impairments of its own, such as chromatic and modal dispersion. Every medium also presents a characteristic impedance, and any discontinuity—a connector, a via, or a stub—reflects part of the signal back toward the source. Matching impedances and taming these reflections is a central discipline of physical-layer design.

From On-Off Signaling to Multilevel Modulation

The simplest line codes are binary. Two-level non-return-to-zero signaling, or NRZ, also called PAM2, represents one bit per symbol by switching between two voltages. For decades this sufficed, but as data rates climbed the required bandwidth grew in step, and copper channels could not pass the resulting frequencies without severe loss. The response was to pack more bits into each symbol. Four-level pulse-amplitude modulation, PAM4, encodes two bits per symbol using four voltage levels, so it carries a given bit rate at half the symbol rate—and therefore half the Nyquist frequency—of NRZ. The trade-off is signal-to-noise ratio: PAM4 divides the same voltage swing into three stacked eyes, each roughly one-third the height of an NRZ eye, which costs on the order of 9.5 decibels of vertical margin and makes equalization and forward error correction essential rather than optional.

The distinction between symbol rate and bit rate is fundamental. Symbol rate, measured in baud, counts symbols per second; bit rate equals the baud rate multiplied by the number of bits carried per symbol. Modern links push both. PCI Express illustrates the progression: generations 1 through 5 used NRZ up to 32 gigatransfers per second, while PCIe 6.0 and the PCIe 7.0 specification released in 2025 adopt PAM4 to reach 64 and 128 gigatransfers per second per lane respectively. High-speed Ethernet follows the same path, with 100-gigabit-per-second lanes built from 56-gigabaud PAM4 and an emerging 224-gigabit-per-second lane using 112-gigabaud PAM4 under development in IEEE 802.3dj and OIF CEI-224G.

Signal Integrity and the Eye Diagram

Because a real channel distorts every symbol, engineers judge link health with the eye diagram, an oscilloscope display that overlays many symbol periods on top of one another. The open region in the center, the eye, measures the margin available to the receiver: its vertical opening is the noise margin, and its horizontal opening is the timing margin. A wide-open eye means bits are easy to distinguish; a closed eye means errors.

Several impairments conspire to close the eye. Frequency-dependent insertion loss smears each symbol into its neighbors, an effect called intersymbol interference. Reflections from impedance discontinuities add delayed copies of the signal. Crosstalk couples energy from adjacent links, and jitter—both random and deterministic timing variation—blurs the moment of decision. At tens of gigabaud, the raw eye at the receiver is often completely closed, and the link works only because equalization reconstructs it. Transmit-side pre-emphasis together with receive-side continuous-time linear, feed-forward, and decision-feedback equalizers undo the channel's filtering, while forward error correction cleans up the residual bit errors that remain.

Composing a Complete Physical Layer

A working physical layer is not any single technique but the careful composition of all of them. Consider a modern Ethernet or PCI Express lane. Information theory sets the ceiling, because the Shannon-Hartley theorem fixes the maximum reliable data rate for the channel's bandwidth and signal-to-noise ratio. Line coding then shapes the bitstream, balancing the signal, guaranteeing transitions for clock recovery, and mapping bits onto PAM4 symbols. Channel coding wraps the data in forward error correction so the link can meet its bit-error-rate target. A serializer-deserializer converts the wide, slow on-chip bus into the fast serial symbol stream and, at the far end, recovers the clock and realigns the words. Finally, equalization at both ends reverses the channel's distortion so the recovered eye is wide enough to slice reliably.

Standards formalize this division of labor. In Ethernet, the physical coding sublayer handles line coding and forward error correction, the physical medium attachment sublayer contains the SerDes, and the physical medium dependent sublayer drives the copper or optics. The topics in this category examine each of these building blocks in turn. Understanding how they fit together is what allows designers to move terabits per second across imperfect physical media while driving bit-error rates down to roughly one error in a trillion bits or fewer.