Electronics Guide

PLA Architecture

In a PLA, input signals enter through buffers that generate both true and complemented versions of each variable. These signals connect to a programmable AND array where product terms (minterms or partial products) are formed by selectively connecting inputs to AND gates. The outputs of the AND gates then feed into a programmable OR array where they can be combined to create any desired sum-of-products expression.

The programming of a PLA occurs through fusible links or programmable connections at the intersections of the AND and OR arrays. Each connection point can be left intact to include that signal in the term, or programmed (blown or disconnected) to exclude it. This dual programmability provides maximum flexibility in implementing arbitrary Boolean functions.

PLA Programming and Notation

PLA programming is typically represented using a notation where each row corresponds to a product term and each column to an input variable or output function. In the AND array, a mark indicates the variable is included in the product term, while in the OR array, marks indicate which product terms contribute to each output.

For example, implementing the function F = AB + AC requires programming the AND plane to create the product terms AB and AC from the input variables A, B, and C, then programming the OR plane to connect both terms to output F. The same product terms can be shared among multiple outputs, maximizing efficiency.

PLA Characteristics

PLAs offer complete flexibility in function implementation but require careful attention to propagation delays and power consumption. The delay through a PLA depends on the number of product terms and outputs, as signals must propagate through both the AND and OR arrays. Power consumption increases with the number of programmed connections due to the current paths created.

Traditional PLAs found extensive use in implementing complex combinational logic, control state machines, and address decoding in early microprocessor systems. While superseded by more advanced architectures for complex designs, PLA principles remain fundamental to understanding all programmable logic devices.

PAL Architecture

In a PAL, the AND array remains fully programmable, allowing arbitrary product terms to be created from the inputs. However, each output connects to a fixed number of product terms through a hardwired OR gate. Typical PAL devices provide 4, 8, or 16 product terms per output, with each product term dedicated to a single output rather than being shareable.

This fixed OR array eliminates one level of programmable interconnection, significantly reducing propagation delay compared to PLAs. The simpler manufacturing process also reduced costs, making PALs economically attractive for volume production.

Output Configurations

PAL devices evolved to include various output configurations beyond simple combinational outputs. Common variants include:

• Combinational outputs: Direct connection from the OR gate to the output pin through a buffer
• Registered outputs: A flip-flop between the OR gate and output, enabling sequential logic implementation
• Registered outputs with feedback: The flip-flop output feeds back to the AND array, supporting state machine design
• Bidirectional pins: Output enable control allows pins to serve as inputs or outputs
• Buried registers: Internal flip-flops not connected to pins, providing additional state storage

PAL Device Families

Manufacturers developed extensive families of PAL devices with standardized pinouts and varying capabilities. The naming convention typically indicated the configuration: for example, a 16L8 provides 16 inputs, combinational (L for logic) outputs, and 8 dedicated outputs, while a 16R8 offers registered (R) outputs. The 22V10, one of the most popular PAL devices, provides versatile (V) macrocells that can be configured as combinational or registered with programmable polarity.

Industry standardization around common PAL pinouts created second-source availability and encouraged widespread adoption. Engineers could design with confidence that compatible devices would remain available from multiple manufacturers.

Erasable Technology

GAL devices use electrically erasable (E2CMOS) cells at each programmable connection point. These cells can be programmed by applying elevated voltages to trap charge in floating gate transistors, and erased by removing the charge electrically. The ability to reprogram the same device repeatedly proved invaluable during development when designs required frequent modifications.

The reprogrammability also enabled in-system programming for some GAL variants, allowing device configuration without removing the chip from the circuit board. This capability proved particularly useful for field updates and configuration changes in deployed systems.

Output Logic Macrocells

GAL devices introduced the output logic macrocell (OLMC) concept, providing configurable output structures that could emulate various PAL output types. A typical OLMC includes a flip-flop, multiplexers for selecting combinational or registered output, programmable polarity selection, and output enable control.

Through macrocell configuration, a single GAL device could replace numerous PAL part numbers. The GAL16V8, for example, could be configured to emulate over a dozen different PAL devices simply by appropriate programming, dramatically simplifying inventory management and design flexibility.

GAL Device Security

GAL devices typically include security features to protect programmed designs from unauthorized copying. A security fuse, when programmed, prevents reading of the device configuration while allowing normal operation. This feature enabled designers to ship products containing GALs without exposing their logic designs to competitors.

The combination of reprogrammability and security made GALs ideal for products requiring field upgradeability while protecting intellectual property in the shipped design.

CPLD Architecture

A CPLD contains multiple function blocks, each resembling a complete PAL device with its own AND array and macrocells. These function blocks connect through a global programmable interconnect matrix that routes signals between blocks and to input/output pins. The architecture maintains the two-level sum-of-products structure within each block while allowing signals to flow between blocks.

Typical CPLDs contain from 2 to over 100 function blocks, with each block providing 8 to 20 macrocells. Total capacities range from a few hundred to several thousand logic gates equivalent, suitable for implementing complete subsystems including state machines, data paths, and interface logic.

Timing Characteristics

CPLDs inherit the predictable timing behavior of their PAL ancestors. Because signals pass through a fixed number of levels (the AND-OR structure within a function block and the global interconnect), propagation delays remain largely independent of the specific logic implemented. This deterministic timing simplifies timing analysis and makes CPLDs well-suited for applications with stringent timing requirements.

Modern CPLDs achieve propagation delays as low as a few nanoseconds from any input to any output, supporting clock frequencies well above 100 MHz. The consistent timing behavior across different designs and programming configurations distinguishes CPLDs from FPGAs where routing variations cause significant timing differences.

Configuration Storage

Most CPLDs use non-volatile configuration storage, retaining their programming when power is removed. Flash-based CPLDs can be reprogrammed in-system through standard interfaces like JTAG (Joint Test Action Group) or proprietary protocols. The instant-on behavior provided by non-volatile storage makes CPLDs ideal for applications where devices must function immediately at power-up.

Some CPLDs include configuration security features similar to GALs, preventing unauthorized reading of programmed designs. Multi-level security on advanced devices provides granular control over which portions of a design can be modified during field updates.

CPLD Applications

CPLDs excel in applications requiring moderate logic complexity with deterministic timing:

• Glue logic integration: Replacing numerous discrete logic chips with a single CPLD
• Bus interface and control: Implementing bus arbitration, address decoding, and protocol conversion
• State machine implementation: Reliable sequential control with predictable timing
• Clock generation and distribution: Creating and buffering multiple clock domains
• Configuration management: Controlling system initialization and mode selection

FPGA Basic Architecture

An FPGA consists of three primary elements: configurable logic blocks (CLBs) that implement logic functions, input/output blocks (IOBs) that interface with external signals, and a programmable interconnection network that routes signals between blocks. The ratio and arrangement of these elements vary among manufacturers and device families, but the fundamental architecture remains consistent.

Logic implementation in FPGAs differs fundamentally from the sum-of-products approach of PLAs and CPLDs. Instead of AND-OR arrays, FPGAs use lookup tables (LUTs) that can implement any Boolean function of their inputs by storing the truth table in memory. This approach provides tremendous flexibility but introduces routing-dependent timing variations.

Logic Capacity and Resources

Modern FPGAs contain thousands to millions of logic elements, supporting implementation of complete systems including processors, memory controllers, communication interfaces, and custom accelerators. Beyond basic logic, contemporary FPGAs incorporate specialized resources:

• Block RAM: Dedicated memory blocks configurable as various widths and depths
• DSP blocks: Hardened multipliers and accumulators for signal processing
• Clock management: PLLs and delay-locked loops for clock generation and distribution
• High-speed transceivers: Multi-gigabit serial interfaces for communication protocols
• Processor cores: Embedded ARM or other processors on some FPGA families

Configuration Methods

Most FPGAs use SRAM-based configuration, requiring external storage to hold the configuration data that is loaded at power-up. The configuration specifies the function of each LUT, the state of each routing switch, and the settings of all other programmable elements. Configuration data can be loaded from:

• Serial flash memory: The FPGA reads configuration data from an attached flash chip
• Parallel flash: Faster loading through wider data paths
• Processor loading: A microcontroller or processor actively loads the configuration
• JTAG: Debug interface doubles as configuration port for development

Some FPGAs use non-volatile configuration storage, either anti-fuse technology for one-time programming or flash memory for reprogrammable designs. These devices offer instant-on operation without external configuration storage.

FPGA Design Flow

Designing for FPGAs involves several stages from specification to configured device:

1. Design entry: Capturing the design through hardware description languages (Verilog, VHDL), schematic capture, or high-level synthesis from C/C++
2. Synthesis: Converting the design description into a netlist of device primitives
3. Implementation: Mapping the netlist to specific FPGA resources, placing elements in physical locations, and routing connections
4. Timing analysis: Verifying that all signal paths meet timing requirements
5. Bitstream generation: Creating the configuration file that programs the FPGA
6. Configuration: Loading the bitstream into the FPGA

LUT Operation

A lookup table is essentially a small memory addressed by the logic function's input variables. For an n-input function, the LUT stores 2^n bits representing the function's output for each possible input combination. When inputs are applied, they form an address that selects the corresponding output bit.

A 4-input LUT (LUT4) can implement any Boolean function of four variables: AND, OR, XOR, multiplexer, and far more complex functions all require exactly one LUT. This uniformity simplifies both design tools and timing analysis compared to variable gate counts in other technologies.

LUT Sizes and Trade-offs

LUT sizes vary among FPGA families, with common configurations including 4-input (LUT4), 5-input (LUT5), and 6-input (LUT6) variants. Larger LUTs implement more complex functions in a single element but consume more silicon area and configuration memory.

The optimal LUT size involves trade-offs: smaller LUTs require more elements and routing for complex functions but waste less capacity on simple functions. Larger LUTs handle complex functions efficiently but underutilize their capacity for simple functions. Modern FPGAs often support fracturable LUTs that can function as one large LUT or two smaller independent LUTs, adapting to design requirements.

LUT Optimization

Synthesis tools automatically map logic functions to LUTs, but understanding the process helps designers write more efficient code. Functions naturally partitioning into independent groups of inputs synthesize more efficiently than highly interconnected logic. Sequential logic benefits from registering intermediate results, breaking long combinational chains into pipelined stages.

Certain functions map particularly well to LUTs. Multiplexers with power-of-two inputs match LUT capacities precisely. Comparators and encoders decompose efficiently into LUT-sized pieces. Arithmetic functions like addition require carry chain resources beyond LUTs for efficiency.

Hierarchical Routing

FPGA routing networks typically use hierarchical structures with multiple wire segment lengths. Local routing connects nearby elements with minimal delay. Regional routing spans clusters of logic elements. Global routing traverses the entire device for long-distance connections and clock distribution.

Each routing level involves programmable switches that connect wire segments. Switch boxes at intersections allow signals to turn corners and change routing levels. The switch patterns and connectivity options significantly impact routability and timing.

Routing Delays

Unlike CPLDs with deterministic timing, FPGA signal delays depend heavily on routing. A signal traveling between adjacent logic elements experiences minimal delay, while crossing the entire device accumulates substantial delay through multiple switch boxes and long wire segments. This variation makes timing closure challenging and requires careful attention during implementation.

Design techniques to manage routing delays include constraining critical paths, using dedicated routing resources for timing-critical signals, and floorplanning to place related logic elements nearby. Pipelining breaks long combinational paths, reducing the cycle time requirement even if adding latency.

Clock Networks

FPGAs include dedicated clock routing networks designed for low skew distribution across the device. These networks use specialized buffers and balanced tree structures to ensure clock edges arrive at all flip-flops nearly simultaneously. Multiple independent clock networks support designs with multiple clock domains.

Clock management resources including PLLs (phase-locked loops) and DLLs (delay-locked loops) generate derived clocks, adjust clock phases, and compensate for insertion delays. Proper use of these resources is critical for reliable high-speed designs.

SRAM-Based Configuration

Most mainstream FPGAs use static RAM cells to control programmable switches and LUT contents. SRAM configuration offers unlimited reprogrammability, fast configuration times, and compatibility with standard CMOS processes for leading-edge performance. However, SRAM is volatile, requiring external configuration storage and a loading process at every power-up.

SRAM-based FPGAs can implement partial reconfiguration, modifying portions of the device while other sections continue operating. This capability enables adaptive systems that change functionality dynamically based on current requirements.

Flash-Based Configuration

Flash-based FPGAs store configuration in non-volatile memory, eliminating external storage requirements and enabling instant-on operation. Configuration persists through power cycles, simplifying system design. Flash technology also provides inherent security since configuration bits cannot be read without special sequences.

Flash-based devices typically support fewer reprogramming cycles than SRAM-based FPGAs (thousands versus unlimited), though this rarely limits practical applications. Some flash FPGAs include small amounts of SRAM configuration for frequently changing portions of designs.

Anti-Fuse Configuration

Anti-fuse FPGAs use programmable elements that start as open circuits and become permanent connections when programmed. This one-time programmable approach provides the highest security (configuration cannot be read or altered) and best radiation tolerance (no single-event upsets affect configuration), making anti-fuse devices preferred for aerospace and military applications.

The inability to reprogram anti-fuse FPGAs requires complete design verification before programming. Once configured, the device permanently implements the programmed design, making development and prototyping more challenging than with reprogrammable alternatives.

Configuration Security

Protecting configuration data from unauthorized access or modification is critical for many applications. Security measures include:

• Bitstream encryption: Configuration data encrypted with AES or other algorithms, decrypted on-chip during loading
• Key storage: Encryption keys stored in battery-backed RAM, eFuses, or other protected memory
• Authentication: Cryptographic verification that configuration data originated from authorized sources
• Tamper detection: Physical security measures that detect and respond to intrusion attempts
• Secure boot: Chain of trust from initial power-up through complete configuration

Complexity Matching

Select device complexity appropriate to the application. Simple glue logic functions consuming a few dozen gates suit PAL/GAL devices or small CPLDs. Moderate complexity designs with hundreds to thousands of gates work well in CPLDs. Complex systems requiring tens of thousands to millions of gates need FPGAs.

Overspecifying device capacity wastes cost and power, while underspecifying leads to resource constraints and potentially degraded performance. Design estimation tools help predict resource requirements before committing to a specific device.

Timing Requirements

Applications with stringent timing requirements benefit from CPLD deterministic timing. When maximum clock frequency and minimum propagation delay are critical, CPLDs' predictable behavior simplifies meeting specifications. FPGAs can achieve similar performance but require careful attention to placement and routing.

For designs with relaxed timing, the flexibility and capacity of FPGAs may outweigh their timing complexity. Modern FPGA tools provide increasingly sophisticated timing closure capabilities, making high-performance FPGA designs achievable with appropriate effort.

Power Considerations

Power consumption varies significantly among programmable logic technologies. Small CPLDs consume microwatts to milliwatts, suitable for battery-powered applications. Larger CPLDs and FPGAs consume tens to hundreds of milliwatts or more. Advanced FPGA power management features including multiple voltage domains and dynamic power reduction can minimize consumption in power-sensitive applications.

Standby power differs dramatically between SRAM-based FPGAs (continuous leakage) and flash-based devices (near-zero standby). For always-on but rarely active applications, flash-based devices offer substantial power advantages.

Cost Analysis

Device cost involves both unit price and development cost. Simple PAL/GAL and CPLD devices cost from under one dollar to several dollars. FPGAs range from a few dollars for basic devices to thousands of dollars for high-end components. Development tool costs similarly range from free for basic capabilities to substantial investments for advanced features.

Total project cost must consider development time, which generally increases with device complexity. The time saved by using a larger, more expensive device that provides design margin may offset the higher unit cost, particularly for low-volume production.

Design Entry Methods

Design entry methods have evolved from Boolean equations through schematic capture to hardware description languages. Modern designs typically use Verilog or VHDL for synthesizable logic, with high-level synthesis (HLS) from C/C++ gaining adoption for algorithm-intensive applications. Schematic capture remains useful for simple designs and visualizing generated logic.

Intellectual property (IP) cores provide pre-designed, verified building blocks that accelerate development. Standard interfaces, processors, and common functions are available as IP, allowing designers to focus on application-specific functionality rather than reinventing standard components.

Simulation and Verification

Thorough verification before implementation saves significant debug time. Functional simulation verifies logical correctness using testbenches that exercise the design under various conditions. Timing simulation adds propagation delays to verify functionality at target operating frequencies.

Formal verification mathematically proves properties of designs without exhaustive simulation. Assertion-based verification embeds correctness properties directly in the design, checked during simulation and synthesis.

Implementation Tools

Implementation tools synthesize, place, and route designs for specific devices. Vendor-specific tools typically provide the best results for their devices, with optimization based on detailed knowledge of device architecture. Third-party synthesis tools offer portability across device families and sometimes superior optimization for specific design styles.

Timing constraints guide implementation tools toward meeting performance requirements. Proper constraint specification is critical: under-constraining allows tools to make suboptimal decisions, while over-constraining may prevent successful implementation.

Interface Adaptation

Programmable logic excels at bridging between different interface standards. Protocol converters, bus width adapters, and voltage level translators implemented in CPLDs or FPGAs provide flexibility during system development and enable integration of components with incompatible interfaces.

Signal Processing

FPGAs with DSP resources implement high-performance signal processing for communications, imaging, and audio applications. Parallel processing capabilities enable throughput impossible with sequential processors, while programmability allows algorithm updates and optimization.

Prototyping and Emulation

Large FPGAs serve as prototyping platforms for ASIC designs, enabling software development and system verification before custom silicon becomes available. FPGA prototypes run orders of magnitude faster than software simulation, dramatically accelerating development cycles.

Production Systems

Beyond prototyping, programmable logic serves in production systems where volumes don't justify custom IC development, where field upgradeability is valuable, or where time-to-market pressures favor programmable solutions over lengthy ASIC development.