Electronics Guide

Sources of Process Variation

Multiple manufacturing steps contribute to the overall variation observed in fabricated circuits:

Lithography variations: The photolithographic process that patterns circuit features cannot achieve perfect fidelity. Focus depth variations across the wafer, lens aberrations, photoresist thickness variations, and exposure dose fluctuations all contribute to line width variations. As feature sizes approach the wavelength of the exposure light, these effects become increasingly pronounced.

Doping variations: Ion implantation processes that establish transistor doping profiles exhibit random variations. The discrete nature of dopant atoms becomes significant at small scales, where statistical fluctuations in the number and placement of dopant atoms within a transistor channel cause random threshold voltage variations.

Etch variations: Plasma etch processes that define feature geometries show rate variations across the wafer and between wafers. Loading effects cause etch rate to depend on local pattern density, leading to systematic variations correlated with layout characteristics.

Deposition and CMP variations: Film thickness variations from deposition processes and planarization non-uniformity from chemical-mechanical polishing affect both transistor and interconnect properties. These variations typically show spatial correlations, with nearby structures experiencing similar deviations.

Systematic vs. Random Variation

Process variations divide into two categories with different implications for design:

Systematic variation: Predictable deviations that correlate with layout patterns, position on the wafer, or other identifiable factors. Examples include etch-rate dependence on pattern density, lens aberrations that affect specific positions in the exposure field, and stress effects from nearby structures. Systematic variations can often be compensated through design rules, layout modifications, or process biasing.

Random variation: Unpredictable deviations that show no correlation with identifiable factors. Random dopant fluctuation is the canonical example: the exact number and position of dopant atoms in a transistor channel is fundamentally random, and this randomness causes threshold voltage variations that cannot be predicted or compensated for individual devices. Random variations must be addressed through statistical design techniques that ensure functionality despite expected variation ranges.

The relative importance of systematic versus random variation has shifted with technology scaling. At older process nodes, systematic variations dominated and could be addressed through careful layout. At modern nodes, random variations, particularly random dopant fluctuation, often dominate, requiring fundamentally different design approaches centered on statistical analysis and guardbanding.

Variation Modeling

Accurate variation models enable designers to predict the impact of manufacturing variation on circuit performance:

Corner models: Traditional corner-based analysis defines process corners representing worst-case combinations of transistor parameters. Typical corners include fast-NMOS/fast-PMOS (FF), slow-NMOS/slow-PMOS (SS), fast-NMOS/slow-PMOS (FS), slow-NMOS/fast-PMOS (SF), and typical-typical (TT). Designs verified at all corners with appropriate voltage and temperature extremes have high confidence of functioning across the expected variation range.

Statistical models: Modern processes require statistical characterization that captures correlations and distributions beyond simple corner models. Monte Carlo simulation using statistical device models provides distribution-aware analysis that identifies designs at risk of parametric failure. These simulations reveal not just whether a design works but what fraction of manufactured parts will meet specifications.

On-chip variation (OCV): Variations within a single die create timing differences between nominally identical paths. OCV analysis applies derating factors to account for these local variations, ensuring that timing constraints are met even when different parts of a chip experience different process conditions. Advanced OCV (AOCV) and parametric OCV (POCV) provide more accurate modeling by considering path depth, distance, and statistical behavior.

Design Techniques for Variation Tolerance

Several design strategies improve robustness against process variation:

Sizing for variation: Using larger transistors reduces the impact of random variations that scale with device area. Critical circuits such as SRAM cells and sense amplifiers often use upsized devices to maintain acceptable yield despite random threshold variations.

Symmetric layout: Matched transistors should use symmetric, common-centroid layouts that expose both devices to the same systematic variations. Interdigitated structures and careful orientation maintain matching despite gradient effects across the layout.

Adaptive circuits: Circuits that sense and compensate for process variations can operate across a wider range than fixed designs. Adaptive body biasing, adjustable supply voltages, and tunable delay elements provide runtime compensation for process variations.

Redundancy: Critical functions can use redundant implementations with voting or selection logic to tolerate individual failures. While area-expensive, redundancy provides robust operation when some circuit instances fall outside acceptable limits.

The Need for OPC

Modern lithography exposes patterns using light with a wavelength of 193 nanometers or, with extreme ultraviolet (EUV), 13.5 nanometers. When feature sizes are comparable to or smaller than the wavelength, diffraction and interference effects distort the aerial image projected onto the photoresist. Without correction, corners round excessively, line ends pull back, dense and isolated features print at different widths, and narrow spaces may fail to resolve entirely.

The printed feature differs from the mask pattern in ways that depend on the surrounding layout context. An isolated line prints differently from a line surrounded by dense parallel features. A line end prints shorter than drawn due to diffraction pulling back the image. These proximity effects must be anticipated and pre-compensated in the mask to achieve the intended printed result.

OPC Techniques

OPC encompasses several complementary techniques:

Rule-based OPC: Simple corrections applied according to geometric rules that identify features requiring modification. Line end extensions, corner serifs, and width biasing based on local pattern density represent typical rule-based corrections. Rule-based OPC runs quickly but may not handle all situations optimally.

Model-based OPC: Iterative optimization using optical and resist models to predict printed contours and adjust mask patterns until predicted results match design intent. Model-based OPC handles complex pattern interactions that rule-based approaches miss but requires significant computational resources. Modern OPC runs may take days on large computing clusters.

Assist features: Sub-resolution assist features (SRAFs) placed near isolated features improve the aerial image by making the effective environment more similar to dense patterns. These features are too small to print but modify the diffraction pattern beneficially. Proper SRAF placement requires careful optimization to achieve maximum benefit without causing printing issues.

Inverse lithography technology (ILT): Mathematical optimization that computes the optimal mask pattern to achieve desired printed results, unconstrained by traditional Manhattan geometry assumptions. ILT produces curvilinear mask features that outperform traditional OPC but require advanced mask writing technology and significantly longer computation time.

OPC Verification

After OPC processing, verification ensures that corrected masks will produce acceptable results:

Contour simulation: Optical and resist models predict the printed contours that will result from the corrected mask. These predicted contours are compared against design intent to identify locations where printed features deviate beyond acceptable tolerances.

Edge placement error: The distance between predicted printed edge positions and intended design edges provides a quantitative measure of OPC quality. Edge placement error must remain within specifications that ensure circuit functionality despite the remaining deviations.

Process window analysis: Lithographic processes operate within a process window defined by acceptable ranges of focus and dose. OPC must produce acceptable results not just at nominal conditions but across the entire process window. Verification analyzes multiple focus and dose combinations to ensure robust printing.

Design Considerations for OPC

Designers can facilitate effective OPC through appropriate layout practices:

Regular structures: Regular, repeating patterns are easier to correct than irregular geometries. Standard cell designs with uniform pitch and consistent features enable more effective OPC than irregular custom layouts.

Minimum spacing compliance: Maintaining adequate spacing between features provides room for OPC modifications and SRAFs. Designs that push minimum spacing limits throughout leave no margin for correction features.

Lithography-friendly design rules: Some foundries provide recommended or restricted design rules that enable better lithographic results. Following these guidelines, even when more aggressive rules are technically allowed, can improve manufacturability.

Hotspot avoidance: Lithographic hotspots are pattern configurations known to cause printing difficulties. Design rule checks can identify and flag hotspot patterns, allowing designers to modify layouts before OPC rather than discovering problems during verification.

Yield Loss Mechanisms

Understanding why chips fail is essential for improving yield:

Random defects: Particles, contamination, and localized process anomalies cause random defects that kill or degrade circuit functionality. These defects follow statistical distributions dependent on defect density and chip area. Larger chips have higher probability of containing a defect, leading to exponentially decreasing yield with increasing die size.

Systematic defects: Layout patterns that are difficult to manufacture cause systematic yield loss. Certain geometries may be prone to bridging, opens, or other failure modes that occur reliably when those patterns are present. Systematic defects affect specific locations predictably rather than striking randomly across the design.

Parametric failures: Parts that function correctly but fail to meet performance specifications reduce effective yield. Timing violations, excessive power consumption, and out-of-specification analog parameters all constitute parametric failures that may be recoverable through speed binning or rejected entirely depending on product requirements.

Yield Modeling

Mathematical models predict yield based on defect density and design characteristics:

Poisson yield model: The simplest model assumes random defects distributed across the wafer according to a Poisson process. Yield decreases exponentially with the product of defect density and chip area. While simplistic, this model captures the fundamental relationship between die size and yield.

Negative binomial model: Defects often cluster rather than distributing uniformly, making Poisson models pessimistic. Negative binomial models account for clustering by introducing a clustering parameter, providing more accurate predictions for processes with non-uniform defect distributions.

Critical area analysis: Not all defects cause failures; only those occurring in critical areas where they can affect functionality matter. Critical area analysis identifies regions where defects of specific types and sizes will cause failures, enabling more accurate yield prediction and guiding design optimization.

Layout Optimization for Yield

Several layout techniques improve defect-limited yield:

Wire spreading: Increasing spacing between wires reduces the probability that a bridging defect will cause a short. Where timing permits, spreading wires beyond minimum spacing improves yield without adding area if the space is otherwise unused.

Via doubling: Using redundant vias in parallel reduces the probability that a single via failure will cause an open circuit. Double or triple vias at transitions between metal layers provide redundancy against via-related defects.

Density uniformity: Maintaining uniform pattern density across the chip improves process uniformity and reduces systematic variation. Fill patterns add dummy features in sparse regions to achieve target density, improving CMP uniformity and etch consistency.

Antenna rule compliance: Long metal runs connected to transistor gates can accumulate charge during plasma processing, potentially damaging gate oxides. Antenna rules limit the ratio of metal area to gate area; designs must comply through wire segmentation, jumpers, or protection diodes.

Redundancy and Repair

Built-in redundancy enables repair of defective elements:

Memory redundancy: SRAM and other memory arrays include spare rows and columns that can replace defective elements. Programmable fuses or antifuses configure the replacement during post-manufacturing testing. This redundancy dramatically improves memory yield at modest area cost.

Logic redundancy: Critical logic paths can include spare elements that substitute for failures. While more complex than memory redundancy, logic repair enables yield improvement for large digital designs.

Self-repair: Some designs include built-in self-repair capability that identifies and maps out defective elements during power-up testing. Self-repair eliminates the need for external test and repair equipment, enabling field repair for high-reliability applications.

The Testability Challenge

Modern integrated circuits contain billions of transistors with limited external access through package pins. Testing requires setting internal nodes to specific values (controllability) and observing the results (observability). Primary inputs and outputs provide direct access, but internal nodes may be many logic levels deep, requiring long sequences of input patterns to control or observe any specific signal.

Without DFT, the test pattern count required for adequate fault coverage grows exponentially with circuit size. Generating and applying these patterns would take longer than practical test times allow. DFT structures break this complexity by providing direct paths to control and observe internal signals, reducing the effective sequential depth seen by automatic test pattern generation tools.

The cost of missing defective parts in production—whether measured in warranty returns, field failures, or customer dissatisfaction—typically far exceeds the cost of thorough testing. DFT investment enables the high fault coverage necessary to ship quality products while keeping test costs manageable.

Testability Metrics

Several metrics quantify testability and test quality:

Fault coverage: The percentage of modeled faults detected by a test pattern set. High fault coverage correlates with high defect detection and low defect escapes. Production test typically targets 95-99% fault coverage, with higher targets for safety-critical applications.

Test pattern count: The number of patterns required to achieve target fault coverage. More patterns mean longer test time and higher test cost. Efficient DFT structures minimize pattern count while maintaining coverage.

Test data volume: The total amount of data that must be transferred to and from the chip during testing. Test data volume affects both test time and the capacity requirements for automatic test equipment.

Diagnostic resolution: The ability to identify the specific defect location when failures occur. High diagnostic resolution enables efficient failure analysis and yield learning. DFT features designed for diagnosis may differ from those optimized purely for detection.

Ad Hoc DFT Techniques

Before structured DFT became standard, designers employed various ad hoc techniques:

Test points: Additional controllability and observability points inserted at strategic locations. Control points force specific values onto internal nodes, while observation points make internal signals visible at outputs. Careful placement improves testability with minimal overhead.

Bus partitioning: Dividing large buses into smaller segments that can be tested independently reduces test complexity. Multiplexers at partition boundaries provide isolation between segments during test.

Initialization: Ensuring that all flip-flops can be reset to known states enables deterministic testing from a known starting point. Lack of initialization forces either longer test sequences or acceptance of reduced coverage for uninitialized logic.

While useful, ad hoc techniques scale poorly to large designs. The design effort required and the achievable coverage improvements are limited compared to structured DFT approaches that have become standard practice.

Stuck-At Fault Model

The stuck-at fault model represents defects that force a signal line permanently to logic 0 (stuck-at-0) or logic 1 (stuck-at-1). This simple model has been the foundation of digital test for decades:

Each signal line in a circuit has two associated stuck-at faults, one for each logic value. A circuit with N signal lines has 2N potential stuck-at faults. Test pattern generation targets these faults by finding input patterns that make the fault effect visible at primary outputs.

The stuck-at model abstracts many physical defects effectively. Open circuits often behave like stuck-at faults when the floating node assumes a consistent value. Some bridging defects behave like stuck-at faults depending on the relative drive strengths of shorted signals. Manufacturing defects in gate inputs typically manifest as stuck-at behavior.

Despite its simplicity, stuck-at testing provides reasonable defect coverage for many defect types. High stuck-at fault coverage correlates with good detection of many physical defect classes, making it a practical baseline for production testing.

Transition Fault Model

Transition faults model defects that prevent signals from changing state, capturing delay defects that stuck-at testing may miss. A slow-to-rise fault prevents a signal from transitioning from 0 to 1 within the allowed time, while a slow-to-fall fault prevents the opposite transition.

Each signal line has two transition faults, corresponding to the two transition directions. Testing transition faults requires applying pairs of patterns: the first pattern initializes the circuit, and the second pattern launches a transition that the fault would delay. The test must be applied at-speed to detect timing-related defects.

Transition fault testing complements stuck-at testing by targeting delay defects that could cause functional failures at operating speed. As process variations increasingly cause timing-related failures, transition fault coverage has become essential for quality testing.

Bridging Fault Model

Bridging faults model shorts between signal lines that should be electrically isolated. When two signals are bridged, their combined behavior depends on the driving gates and the nature of the short:

Dominant bridging: One signal dominates, forcing the other to its value regardless of intended logic. This model assumes unequal drive strengths where the stronger driver controls both signals.

Wired-AND/OR bridging: The bridged signals assume the AND or OR of their intended values, modeling resistive shorts where both drivers contribute. The specific behavior depends on technology characteristics.

Bridging fault testing requires activating both bridged signals to different values and observing the resulting conflict. The number of potential bridging faults grows quadratically with circuit size, making exhaustive testing impractical. Testing typically targets layout-extracted bridges between physically adjacent signals most likely to short.

Path Delay Fault Model

Path delay faults model cumulative delay along complete timing paths rather than focusing on individual elements. A path delay fault causes excessive delay along a specific path from input to output, potentially causing setup time violations even when individual gate delays are within specifications.

The number of paths in a circuit grows exponentially with circuit depth, making exhaustive path delay testing intractable for all but small circuits. Testing typically focuses on critical and near-critical paths where timing is most constrained. These paths are most likely to fail if delay variations push them beyond timing margins.

Path delay testing uses two-pattern tests similar to transition fault testing but focuses on sensitizing specific paths. Robust path delay tests ensure that the transition propagates only along the target path; non-robust tests accept that other paths may also contribute to the observed delay.

Fault Model Selection

Production test programs typically combine multiple fault models to maximize defect detection:

• Stuck-at patterns provide a baseline that catches many defect types efficiently
• Transition fault patterns detect delay defects and gross timing failures
• Bridging fault patterns target shorts between adjacent signals
• Path delay patterns verify critical timing paths at speed

The combination of fault models addresses defect classes that individual models might miss, providing comprehensive defect coverage while keeping total pattern count manageable.

Scan Architecture

A scan chain connects flip-flops sequentially, allowing test data to shift in through a scan input pin and shift out through a scan output pin. During normal operation, flip-flops function conventionally, capturing data from their functional inputs. During scan mode, flip-flops connect serially, enabling direct loading and observation of all register contents.

Each scan flip-flop includes a multiplexer selecting between functional data input and scan chain input. A global scan enable signal controls this selection. When scan enable is asserted, a clock pulse shifts data one position along the chain. When scan enable is deasserted, clock pulses capture functional data as in normal operation.

The basic scan test sequence for stuck-at testing follows a shift-capture-shift pattern:

1. Shift in: Load all flip-flops with desired test values by shifting data through the scan chain
2. Capture: Deassert scan enable and apply one functional clock to capture combinational responses
3. Shift out: Shift captured responses out for comparison while simultaneously shifting in the next pattern

Scan Insertion Flow

Scan insertion typically occurs during logic synthesis or as a post-synthesis transformation:

Flip-flop replacement: Standard flip-flops are replaced with scan equivalents containing the test multiplexer. The scan flip-flop has identical functional behavior but includes the additional scan input and multiplexer control.

Chain construction: Scan flip-flops are connected into chains based on physical proximity and timing constraints. Chain length balancing ensures roughly equal shift times across all chains. Clock domain boundaries constrain chain construction to avoid mixing flip-flops clocked by different signals.

Compression integration: Modern designs typically include scan compression logic that reduces test data volume. Compressors connect between scan pins and internal chains, encoding/decoding test data to reduce pin count and shift cycles.

Design rule checking: Automated checks verify that all flip-flops are included in scan chains, chain connectivity is correct, and timing constraints for scan operations are met.

Scan Testing Considerations

Several factors affect scan test implementation and effectiveness:

Area overhead: Scan flip-flops are larger than standard flip-flops due to the test multiplexer. Typical overhead ranges from 5-15% of total cell area, depending on the ratio of sequential to combinational logic. The multiplexer also adds delay to the functional data path.

Timing impact: The scan multiplexer adds delay in the functional data path that must be considered during timing analysis. Additionally, the scan chain itself must meet timing constraints for reliable shifting. Hold time violations during shift can corrupt test data.

Power during scan: Shifting test patterns causes many flip-flops to toggle simultaneously, creating power consumption spikes that may exceed normal operation. Excessive scan power can cause voltage drops that affect circuit operation or damage the device. Power-aware scan techniques address this concern.

Multiple clock domains: Designs with multiple asynchronous clock domains require separate scan chains for each domain or specialized techniques to safely cross domain boundaries during test. Mixing flip-flops from different domains in a single chain can cause incorrect capture or shift behavior.

At-Speed Scan Testing

At-speed testing applies the second clock pulse of a two-pattern test at the functional clock frequency, enabling detection of timing-related defects:

Launch-off-shift (LOS): The last shift pulse launches the transition, and the capture pulse occurs at functional speed. This method is simple to implement but the shift clock may not accurately represent functional conditions.

Launch-off-capture (LOC): A functional-speed capture launches the transition, followed immediately by another functional-speed capture. Both clock pulses operate at speed, providing more realistic testing conditions. LOC requires two functional clocks after shifting, slightly increasing test time.

At-speed testing reveals delay defects that slow-speed testing misses. Process variations increasingly cause timing failures that manifest only at operating speed, making at-speed test essential for modern designs. The test patterns for at-speed testing typically target transition or path delay fault models.

BIST Architecture

A typical BIST implementation includes three main components:

Pattern generator: Produces test patterns applied to the circuit under test. Linear feedback shift registers (LFSRs) are commonly used, generating pseudo-random patterns that provide good fault coverage with simple hardware. Deterministic BIST stores specific patterns to achieve higher coverage for hard-to-detect faults.

Response analyzer: Compresses circuit responses into a signature for comparison. Multiple-input signature registers (MISRs) compute a cyclic redundancy check of the response stream. Matching signatures indicate correct responses; mismatches indicate failures. The probability of aliasing (incorrect signature despite errors) is negligibly small for practical signature lengths.

BIST controller: Sequences the test operation, managing pattern count, clock application, and pass/fail determination. The controller initializes the LFSR and MISR, runs the specified number of patterns, and compares the final signature against the expected value.

Logic BIST

Logic BIST tests random logic by applying pseudo-random patterns and compacting responses:

Pseudo-random pattern testing: LFSR-generated patterns provide approximately 80-90% stuck-at fault coverage for typical circuits. The randomness ensures broad exploration of the input space, detecting many faults without explicit pattern targeting. However, random patterns may not efficiently test certain structures like highly encoded state machines or arithmetic circuits.

Weighted random patterns: Biasing pattern generators to produce certain values more frequently can improve coverage for circuits with unequal sensitivity to ones and zeros. Weight sets are computed based on fault simulation to identify beneficial biases.

Deterministic BIST: Combining pseudo-random testing with stored deterministic patterns addresses faults that random patterns cannot detect. The deterministic patterns target specific hard faults identified during fault simulation. Various encoding schemes minimize the storage required for deterministic patterns.

Test points for BIST: Inserting control and observation points specifically to improve random pattern testability can significantly increase coverage. These points address random-pattern-resistant faults by making internal signals more easily controlled or observed.

Memory BIST

Memory BIST tests embedded memories using march algorithms that systematically write and verify patterns:

March tests: A march element writes or reads a value to/from all memory locations in a specific order (up or down addressing). March tests concatenate multiple elements with different patterns and orders to detect various fault types. The march sequence determines which faults can be detected.

Common march algorithms: MATS+ detects stuck-at faults with minimal patterns. March C- detects coupling faults where writing one cell affects another. March LR targets realistic physical defects based on defect analysis. More complex algorithms detect more fault types but require more test time.

Memory BIST controller: Generates addresses, data patterns, and control signals according to the programmed march algorithm. Most controllers are programmable, allowing different algorithms for different memory types or test phases. Address scrambling may be included to match logical and physical addressing.

Built-in repair: Memory BIST often integrates with redundancy repair, identifying failing rows or columns and programming spare elements to replace them. This repair occurs during production test or power-up, transparently improving memory yield.

BIST Considerations

Implementing BIST requires balancing benefits against costs:

Area overhead: BIST circuitry adds area for pattern generators, response analyzers, controllers, and test points. For small designs, BIST overhead may exceed the cost of external testing. For large memories or complex logic, the overhead becomes relatively smaller.

Test coverage: Logic BIST with random patterns typically achieves lower fault coverage than deterministic automatic test pattern generation. Achieving coverage comparable to external test requires additional investment in deterministic BIST or extensive test point insertion.

At-speed capability: BIST naturally supports at-speed testing since the test clock is generated on-chip. This advantage is particularly valuable for high-speed interfaces and timing-critical circuits that are difficult to test at speed from external equipment.

Field testing: BIST enables testing of deployed systems without test access equipment. This capability supports manufacturing test, system diagnostic, and maintenance testing throughout product lifetime.

Diagnosis Approaches

Several techniques locate faults based on test failure data:

Effect-cause diagnosis: Working backward from observed failures to potential causes, effect-cause diagnosis identifies fault sites that could explain the observed symptom patterns. For each failing pattern, the diagnosis tool traces back from the failing output through the circuit to find candidate fault locations consistent with the observation.

Cause-effect diagnosis: Starting from the fault model, cause-effect diagnosis simulates each potential fault and compares predicted behavior against observed failures. Faults whose simulated behavior matches the actual failure pattern are diagnosed candidates. This approach is computationally intensive but thorough.

Statistical diagnosis: When many failing chips are available, statistical analysis identifies fault locations that correlate with observed failure patterns across the population. This approach can identify systematic defects affecting specific layout locations or pattern types.

Diagnosis Resolution

Diagnosis resolution describes how precisely a fault can be located:

Gate-level resolution: Identifying the specific gate or net containing the defect. This resolution enables targeted failure analysis and correlates well with physical defect location.

Net-level resolution: Identifying a specific interconnect net, potentially spanning multiple gates. Net-level diagnosis is appropriate for interconnect defects like opens and shorts.

Region-level resolution: Narrowing the defect to a physical region rather than a specific element. While less precise, region-level diagnosis still guides failure analysis by limiting the search area.

Higher resolution requires more diagnostic data, typically meaning more failing patterns or patterns specifically designed for diagnosis. Production test patterns optimized for detection may not provide optimal diagnostic resolution.

Diagnosis for Yield Learning

Systematic diagnosis across production supports yield improvement:

Defect Pareto: Aggregating diagnosis results across many failing chips identifies the most common defect locations and types. This Pareto guides process improvement efforts toward the highest-impact issues.

Layout correlation: Correlating diagnosed defects with layout patterns identifies systematic yield detractors. Certain layout configurations may be more defect-prone, guiding design rule refinement or layout optimization.

Process monitoring: Tracking diagnosed defect types over time reveals process drift or equipment issues. Changes in defect distributions can indicate process problems before they severely impact yield.

Volume diagnosis: Automated diagnosis of large volumes of failing parts enables statistical analysis that would be impractical with manual failure analysis alone. Volume diagnosis accelerates yield learning by providing statistically significant defect data.

Failure Analysis Support

Diagnosis guides physical failure analysis:

Localization: Diagnosis results direct failure analysis equipment to specific locations on the die, reducing search time for defects. Without diagnosis, finding a defect in a large chip can require extensive scanning.

Failure hypothesis: Diagnosed fault type suggests what kind of defect to look for. A diagnosed stuck-at-1 fault suggests a short to power supply; an open fault suggests a broken interconnect or via.

Cross-section targeting: Physical analysis techniques like focused ion beam cross-sectioning benefit from precise defect location. Diagnosis enables cross-sectioning exactly at the fault site rather than searching by trial and error.

Root cause correlation: Correlating diagnosis results with physical failure analysis findings validates the diagnosis methodology and builds confidence in volume diagnosis without exhaustive physical verification.