Electronics Guide

Operating Principle

In a current feedback amplifier, the inverting input presents low impedance and senses the error current flowing into the feedback network. The non-inverting input is a high-impedance buffer that sets the reference voltage. The output stage is a transimpedance amplifier that converts the error current to an output voltage.

The key insight is that bandwidth is determined by the transimpedance (Z(s)) and feedback resistor (Rf), not by the gain-bandwidth product constraint of voltage feedback amplifiers:

• Closed-loop bandwidth is approximately: f_3dB = 1/(2 pi Rf Ct), where Ct is the internal compensation capacitance
• Gain is set by the ratio Rf/Rg, where Rg is the gain-setting resistor
• Increasing gain by reducing Rg does not significantly reduce bandwidth

Advantages Over Voltage Feedback

Current feedback amplifiers offer several advantages for high-speed applications:

• Constant bandwidth with gain: Unlike voltage feedback amplifiers where bandwidth decreases as gain increases, CFAs maintain nearly constant bandwidth across typical gain ranges of 1 to 10
• High slew rate: The Class AB output stage can source and sink large currents, enabling slew rates of several thousand volts per microsecond
• Fast settling time: Reduced phase shift in the feedback loop results in faster settling to final value
• Low distortion at high frequencies: The current-mode operation reduces the effects of nonlinear input capacitance

Design Considerations

Working with current feedback amplifiers requires attention to specific design rules:

• Feedback resistor selection: Rf must be within the manufacturer-specified range (typically 500 ohms to 1.5 kilohms); too low causes peaking and instability, too high reduces bandwidth excessively
• No capacitive feedback: Placing capacitance directly in the feedback path causes instability; use resistor-capacitor combinations with series resistance
• Inverting input loading: Capacitance on the inverting input degrades stability; minimize stray capacitance
• Symmetrical layout: Match parasitic capacitances on both inputs to minimize offset and distortion

Application Circuits

Current feedback amplifiers excel in several high-speed applications:

• Cable drivers: The high slew rate and current output capability make CFAs ideal for driving 50-ohm or 75-ohm transmission lines
• Active filters: CFAs enable active filters at frequencies where voltage feedback amplifiers cannot provide adequate gain
• Video distribution: CFAs can drive multiple outputs while maintaining signal quality
• DAC output stages: The fast settling time improves DAC throughput and reduces glitch energy

Basic Configuration

The fundamental transimpedance amplifier places a feedback resistor Rf across an operational amplifier. The transimpedance gain is simply:

• Vout = -Iin times Rf

The input appears as a virtual ground, meaning the source sees low impedance regardless of the large feedback resistance. This is critical for photodiode applications where the diode capacitance would otherwise form a pole with a high-impedance load.

Bandwidth and Stability

The input capacitance (typically the photodiode junction capacitance Cd) combines with the feedback resistor to create a zero in the noise gain, potentially causing instability. The bandwidth-stability trade-off is governed by:

• The noise gain zero occurs at: f_z = 1/(2 pi Rf Cd)
• For stability, the amplifier gain-bandwidth product (GBW) must exceed the noise gain at the crossover frequency
• A feedback capacitor Cf in parallel with Rf adds a pole that can compensate the zero

Optimal compensation sets Cf such that the noise gain intersects the open-loop gain at a 20 dB per decade rate:

• Cf = sqrt(Cd/(2 pi Rf GBW)) for maximally flat response

Noise Analysis

Transimpedance amplifier noise has several components:

• Johnson noise of Rf: In = sqrt(4kT/Rf) A/sqrt(Hz); fundamental limit set by the feedback resistor
• Amplifier voltage noise: Multiplied by the noise gain at high frequencies; dominant noise source in wideband TIAs
• Amplifier current noise: Usually negligible in FET-input amplifiers but significant with bipolar inputs
• Photodiode shot noise: Signal-dependent noise from the photocurrent

For minimum noise, use the largest Rf that meets bandwidth requirements and select an amplifier with low voltage noise density.

High-Speed TIA Design

Multi-gigahertz transimpedance amplifiers for fiber optic applications require specialized approaches:

• Regulated cascode input: Provides low input impedance while isolating the photodiode capacitance from the gain stage
• Inductive peaking: Series inductors extend bandwidth beyond the RC limit
• Cherry-Hooper topology: Cascaded transconductance and transimpedance stages achieve high gain-bandwidth product
• Differential architectures: Balanced designs reject common-mode noise and power supply interference

Characteristics and Specifications

Key parameters for limiting amplifiers include:

• Small-signal gain: Typically 30 to 60 dB to amplify weak signals to full output swing
• Limiting threshold: The input level at which output begins to saturate
• Output swing: Usually matched to downstream logic levels (LVDS, CML, LVPECL)
• Input sensitivity: Minimum input amplitude for correct operation, typically a few millivolts
• Overload recovery: Time to return to normal operation after a large input transient

Architecture

High-speed limiting amplifiers use cascaded gain stages with soft limiting:

• Differential pairs with resistive loads: Each stage provides 10 to 15 dB gain until the differential pair saturates
• Offset cancellation: DC offset in early stages would saturate later stages; feedback loops null the offset
• Gain peaking: Inductive loads extend bandwidth by compensating capacitive roll-off
• Output buffer: Final stage provides standard logic levels and drive capability

Applications

Limiting amplifiers serve critical functions in high-speed systems:

• Optical receivers: Convert weak, variable TIA outputs to digital levels
• Clock and data recovery: Provide amplitude-independent edges for timing extraction
• Frequency synthesizers: Square up sine waves for phase detector inputs
• Radar and communications: Process signals with large dynamic range

Cable and Trace Characteristics

Transmission media exhibit several loss mechanisms:

• Skin effect: Conductor resistance increases as sqrt(frequency), causing high-frequency attenuation
• Dielectric loss: Proportional to frequency, adds to conductor loss
• Dispersion: Different frequency components travel at different velocities, causing pulse spreading
• Reflections: Impedance discontinuities cause signal reflections that corrupt data

At gigabit rates, even short traces exhibit significant loss. A 10-inch FR4 trace at 5 Gbps may attenuate the signal by 10 dB or more.

Driver Design

High-speed cable drivers must deliver clean signals with controlled impedance:

• Output impedance matching: Source termination (typically 50 ohms) prevents reflections from the far end returning to corrupt subsequent bits
• Rise time control: Excessive rise time causes intersymbol interference; too fast causes EMI
• Pre-emphasis: Boosting high-frequency components at the transmitter compensates for cable attenuation
• Differential signaling: Reduces common-mode noise and allows lower voltage swings

Passive Equalization

Simple passive networks can compensate moderate cable losses:

• High-pass shelving filter: Attenuates low frequencies to match the cable's attenuation of high frequencies
• Series RC network: Creates a zero that boosts high-frequency response
• Cable simulation: The equalizer transfer function is the inverse of the cable response

Passive equalization introduces loss at low frequencies, reducing overall signal amplitude. It is suitable for moderate data rates and cable lengths.

Active Equalization

High-speed serial links employ sophisticated active equalization:

• Continuous-time linear equalizer (CTLE): Active filter with programmable high-frequency boost; first stage of receiver equalization
• Decision feedback equalizer (DFE): Uses previous bit decisions to cancel intersymbol interference; effective against reflections
• Adaptive equalization: Algorithms adjust equalizer coefficients based on received signal quality
• Feed-forward equalizer (FFE): Transmitter-side equalization using a finite impulse response filter

Bandwidth and Flatness Requirements

Video bandwidth requirements depend on the format:

• Standard definition: 5 to 6 MHz for composite video
• Component video (480p/576p): 10 to 15 MHz per channel
• High definition (1080i/720p): 30 to 40 MHz per channel
• Full HD (1080p): 75 to 100 MHz per channel

Gain flatness of plus or minus 0.1 dB is typically required to avoid visible artifacts. Even slight gain variations cause color shifts and brightness non-uniformity.

DC Accuracy and Clamping

Video signals carry brightness information as DC levels:

• Black level: Corresponds to blanking level; must be accurately preserved
• Sync tips: Define the timing reference; must not be compressed or clipped
• White level: Maximum brightness; headroom required for super-white

AC coupling removes the DC information, requiring restoration through clamping circuits that establish the black level during blanking intervals. DC-coupled amplifiers avoid this complexity but require careful offset management.

Differential Gain and Phase

Video amplifier nonlinearity manifests as differential gain and phase errors:

• Differential gain: Change in chrominance amplitude with luminance level; causes color saturation shifts with brightness
• Differential phase: Change in chrominance phase with luminance; causes color hue shifts with brightness
• Acceptable limits: Less than 0.1 percent differential gain, less than 0.1 degree differential phase for broadcast quality

Achieving these specifications requires high-linearity amplifiers with adequate slew rate to handle the highest-frequency components.

Cable Driving

Video signals are typically distributed over 75-ohm coaxial cable:

• Impedance matching: 75-ohm source termination prevents reflections
• Current capability: Must drive 75-ohm load to standard video levels (1 Vpp for composite)
• Multiple outputs: Distribution amplifiers drive several cables from one source
• Back termination: Series resistor at the driver matches cable impedance

Pulse Fidelity Parameters

Pulse response quality is measured by several parameters:

• Rise time: Time for the output to transition from 10 percent to 90 percent of final value
• Overshoot: Percentage the output exceeds the final value before settling
• Droop: Decay of the pulse top during the pulse duration; caused by insufficient low-frequency response
• Settling time: Time for the output to remain within a specified percentage of final value

Bandwidth and Rise Time Relationship

For a first-order system, rise time and bandwidth are inversely related:

• Rise time (10 percent to 90 percent) approximately equals 0.35 / bandwidth (Hz)

For cascaded stages, rise times add in quadrature:

• Total rise time = sqrt(t1^2 + t2^2 + t3^2 + ...)

This means the slowest stage dominates overall rise time, and each additional stage degrades performance by less than linear addition would suggest.

Pulse Shaping Techniques

Various techniques modify pulse characteristics:

• Differentiation: Converts a step to a pulse; used for edge detection
• Integration: Smooths pulses and reduces high-frequency noise
• Delay line shaping: Creates pulse widths equal to the delay time
• Gaussian shaping: Optimizes signal-to-noise ratio in nuclear pulse processing

Operating Principle

A TDR system launches a fast edge into the transmission line under test and monitors the reflected waveform:

• A step or pulse generator produces a fast transition (typically less than 50 ps)
• The signal travels down the transmission line at the propagation velocity
• Impedance discontinuities cause reflections proportional to the impedance mismatch
• The reflected signal returns to the source after a round-trip delay
• A sampling oscilloscope captures both incident and reflected waveforms

Interpreting TDR Waveforms

The reflection coefficient relates the reflected and incident amplitudes:

• Rho = (Zl - Z0)/(Zl + Z0), where Zl is the load impedance and Z0 is the line impedance

Common TDR signatures include:

• Open circuit: Positive reflection equal to incident amplitude
• Short circuit: Negative reflection equal to incident amplitude
• Higher impedance: Step up in the waveform
• Lower impedance: Step down in the waveform
• Capacitive discontinuity: Negative spike followed by exponential recovery
• Inductive discontinuity: Positive spike followed by exponential decay

Resolution and Accuracy

TDR measurement quality depends on system rise time:

• Spatial resolution: Approximately (rise time / 2) times propagation velocity; 50 ps rise time gives about 4 mm resolution
• Closely spaced discontinuities: Reflections overlap if separation is less than the spatial resolution
• Impedance accuracy: Depends on pulse amplitude accuracy and oscilloscope calibration

Differential TDR

Modern high-speed links use differential signaling, requiring differential TDR:

• Differential mode: Anti-phase signals measure odd-mode impedance
• Common mode: In-phase signals measure even-mode impedance
• Mode conversion: Asymmetries convert differential signals to common mode, causing EMI and crosstalk

Eye Diagram Construction

An eye diagram is created by:

• Triggering an oscilloscope on the recovered clock
• Setting the horizontal timebase to display one or two bit periods
• Acquiring many waveform traces representing all bit patterns
• Overlaying the traces to form the composite eye pattern

The resulting display shows all possible signal trajectories, with the open area in the center representing the valid sampling region.

Key Eye Diagram Measurements

Several quantitative metrics characterize eye quality:

• Eye height: Vertical opening at the sampling point; indicates voltage margin for noise
• Eye width: Horizontal opening at the decision threshold; indicates timing margin
• Eye amplitude: Vertical distance between average high and low levels
• Jitter: Horizontal variation in edge position; reduces timing margin
• Rise and fall times: Edge transition speeds; affect eye opening and EMI
• Crossing percentage: Vertical position where rising and falling edges cross; should be near 50 percent

Sources of Eye Closure

Several phenomena degrade the eye opening:

• Intersymbol interference (ISI): Memory effects cause current bit response to depend on previous bits
• Random jitter: Noise-induced timing variations; unbounded Gaussian distribution
• Deterministic jitter: Pattern-dependent timing variations; bounded but data-dependent
• Duty cycle distortion: Asymmetry between high and low times
• Crosstalk: Coupling from adjacent signals adds noise and jitter

Optimization Techniques

Improving eye diagram quality involves addressing specific degradation mechanisms:

• Transmitter pre-emphasis: Boost high-frequency content to compensate channel loss; parameters include boost amount and number of taps
• Receiver equalization: CTLE and DFE work together to open the eye; CTLE handles frequency-dependent loss, DFE cancels reflections
• Impedance control: Maintaining 100-ohm differential impedance minimizes reflections
• Power supply decoupling: Reduces supply-induced jitter and noise
• Ground plane integrity: Continuous reference planes reduce crosstalk and mode conversion

Eye Diagram Masks

Standards define mask regions that the eye must not enter:

• Inner mask: Central region defining minimum eye opening
• Outer masks: Upper and lower boundaries limiting overshoot
• Transition time masks: Side regions limiting edge position variation

A compliant signal has zero hits within the mask region when tested with a specified number of unit intervals. Different standards (Ethernet, USB, PCIe) define specific mask geometries appropriate for their requirements.

Transmission Line Routing

High-speed traces must be treated as transmission lines:

• Controlled impedance: Maintain consistent trace width and reference plane spacing
• Length matching: Differential pairs and parallel buses must have matched electrical lengths
• Reference plane continuity: Avoid splits and cuts in ground and power planes under high-speed traces
• Via transitions: Use back-drilling or blind vias to minimize stub length

Component Placement

Strategic component placement minimizes signal path length and parasitic effects:

• Minimize trace length: Shorter traces have lower loss and fewer discontinuities
• Decoupling capacitor placement: Position capacitors between power pins and the nearest ground via
• Thermal considerations: Allow adequate spacing for heat dissipation from high-speed drivers
• EMI containment: Group high-speed circuits to minimize the radiation area

Power Distribution

High-speed circuits demand clean, low-impedance power:

• Multiple capacitor values: Each value provides low impedance over a different frequency range
• Plane capacitance: Closely spaced power and ground planes provide high-frequency decoupling
• Current return paths: Signal currents return through the reference plane directly beneath the trace
• Avoiding plane splits: Signals crossing plane splits suffer impedance discontinuities and radiation