Electronics Guide

Fundamentals of Time-Domain Processing

Understanding time-based signal processing requires appreciation of the fundamental trade-offs between voltage-domain and time-domain representations, as well as the basic building blocks that enable temporal signal manipulation.

Time as an Information Carrier

Encoding information in time rather than voltage amplitude offers several key advantages:

• Voltage headroom independence: Time intervals are fundamentally independent of supply voltage, making time-based circuits naturally suited to low-voltage operation. A 10ps timing edge carries the same information whether the signal swings 0.5V or 5V
• Digital compatibility: Time-encoded signals use digital-like edges and transitions, enabling straightforward interfacing with digital processing systems and leveraging digital synthesis and verification tools
• Technology scaling benefits: As transistor geometries shrink, switching speeds improve while analog precision degrades. Time-based circuits convert this liability into an advantage by exploiting faster transitions
• Noise immunity: Time-encoded signals are relatively immune to amplitude noise that would corrupt voltage-domain representations, particularly for large signals where edge timing is determined by threshold crossings
• Process variation tolerance: Many time-based architectures use ratio-matching and self-calibration techniques that cancel systematic process variations

Time Resolution and Accuracy

The precision achievable in time-domain processing depends on several fundamental factors:

• Edge rate limitations: Finite signal transition times blur the precise moment of threshold crossing. Faster edge rates improve timing precision but require higher bandwidth circuits and consume more power
• Jitter sources: Random noise in oscillators, delay elements, and switching circuits creates timing uncertainty (jitter) that limits resolution. Thermal noise in transistors ultimately bounds achievable precision
• Quantization effects: Digital time measurement inherently quantizes continuous time into discrete intervals. The quantization step size determines minimum resolvable time differences
• Reference stability: Time measurements require stable references, typically derived from crystal oscillators. Reference jitter and drift contribute directly to measurement uncertainty
• Metastability: When time intervals approach the resolution limit of digital circuits, metastability can occur, requiring careful architectural consideration

Basic Time-Domain Building Blocks

Several fundamental circuit elements form the foundation of time-based processing systems:

• Delay elements: Fixed or variable delay cells that postpone signal transitions by controlled amounts form the basis of most time-domain circuits. These range from simple inverter chains to precision voltage-controlled delay lines
• Phase detectors: Circuits that measure the time difference between edges of two signals, typically producing either a pulse whose width encodes the time interval or a voltage proportional to phase difference
• Edge generators: Circuits that create precisely timed edges from input signals, often using threshold crossing detection, regenerative latching, or Schmitt trigger action
• Time-to-amplitude converters: Circuits that convert time intervals into voltage or current magnitudes for further processing or measurement
• Amplitude-to-time converters: The complement of time-to-amplitude converters, these circuits encode voltage levels as timing information, forming the input stage of time-based ADCs

Time-to-Digital Converters

Time-to-digital converters (TDCs) form the core measurement engine in time-based systems, transforming temporal intervals into digital codes. These circuits have become essential components in applications ranging from laser ranging and time-of-flight imaging to all-digital phase-locked loops and time-based analog-to-digital conversion.

Counter-Based TDC Architecture

The simplest TDC architecture uses a high-frequency clock to count periods within the measured time interval:

• Operating principle: A digital counter increments on each clock edge while a gate signal, derived from the measured time interval, enables counting. The final count represents the interval in units of the clock period
• Resolution limits: Counter-based TDCs achieve resolution equal to the clock period. Practical clock frequencies of several hundred MHz limit resolution to a few nanoseconds
• Quantization error: The asynchronous relationship between the measured interval and the clock introduces quantization error up to plus or minus one-half clock period
• Advantages: Counter-based TDCs offer unlimited dynamic range (limited only by counter width), excellent linearity, and straightforward implementation using standard digital cells
• Power and area: High-frequency counting requires significant power for clock distribution and counter operation, with area scaling linearly with bit width

Delay-Line TDC Architecture

Delay-line TDCs achieve sub-gate-delay resolution by using distributed sampling along a tapped delay line:

• Basic structure: A cascade of delay elements (typically inverters or buffers) creates a series of progressively delayed versions of the start signal. The stop signal samples all taps simultaneously via parallel flip-flops
• Resolution: The minimum resolvable time equals the delay per stage, typically 10-50ps in modern CMOS processes. This represents an order of magnitude improvement over counter-based approaches
• Thermometer-to-binary encoding: The flip-flop outputs form a thermometer code that must be converted to binary representation. Edge detection logic identifies the transition point
• Dynamic range limitations: Delay-line TDCs have limited dynamic range determined by the number of stages. Typical implementations provide ranges from hundreds of picoseconds to tens of nanoseconds
• Nonlinearity sources: Variations in delay per stage due to process gradients, supply voltage drops, and temperature differences create differential and integral nonlinearity

Vernier TDC Architecture

Vernier TDCs achieve even finer resolution by exploiting the difference between two slightly mismatched delay lines:

• Operating principle: Two delay lines with slightly different stage delays process the start and stop signals. The faster line gradually catches up to the slower line, with the number of stages required for coincidence encoding the input time difference
• Resolution enhancement: The vernier principle amplifies time differences, achieving resolution equal to the delay difference rather than the absolute delay. With 5% mismatch, a 20ps gate delay yields 1ps resolution
• Coincidence detection: Arbiters or phase detectors at each tap determine when the two signals align, generating the stop condition for counting
• Conversion time: Vernier TDCs require multiple delay stages to complete conversion, with conversion time proportional to the input time interval divided by the vernier gain
• Mismatch sensitivity: The resolution depends on maintaining precise delay differences between the two lines, making the design sensitive to systematic and random mismatch

Hybrid and Coarse-Fine TDC Architectures

Practical TDCs often combine multiple techniques to achieve both wide dynamic range and fine resolution:

• Coarse-fine approach: A counter measures the integer number of clock periods while a delay-line or vernier TDC interpolates within each period. This combines the unlimited range of counters with the fine resolution of interpolation
• Nutt method: Start and stop interpolators independently measure residual times to the nearest clock edges, avoiding the need for high-frequency counting during the entire interval
• Multi-stage interpolation: Successive interpolation stages progressively refine the measurement, with each stage resolving fewer bits at higher precision
• Resolution versus power trade-off: Hybrid architectures enable optimization of the power-resolution trade-off by using power-efficient counters for coarse measurement and higher-power interpolators only for fine resolution

TDC Performance Optimization

Achieving optimal TDC performance requires careful attention to several design aspects:

• Calibration techniques: Background calibration continuously measures and corrects delay variations, enabling stable performance despite temperature changes and aging effects
• Dithering and averaging: Adding controlled timing dither and averaging multiple measurements can reduce effective quantization noise below the single-shot resolution
• Layout considerations: Matched routing, common-centroid arrangements, and shielding minimize systematic mismatches. Delay line orientation relative to process gradients affects linearity
• Power supply sensitivity: Delay elements exhibit significant supply voltage dependence. Regulated or filtered supplies and differential delay structures reduce supply-induced errors
• Single-shot versus averaging precision: Many TDC applications benefit from averaging multiple measurements, relaxing single-shot resolution requirements in favor of improved throughput

Voltage-Controlled Delay Lines

Voltage-controlled delay lines (VCDLs) are fundamental building blocks that produce output signals delayed from their inputs by amounts determined by control voltages. These circuits enable phase-locked loops, delay-locked loops, clock generation, and time-domain signal processing.

Current-Starved Delay Elements

The most common VCDL implementation uses current-starved inverters:

• Operating principle: Additional transistors in series with the supply or ground limit the charging and discharging currents available to the inverter load capacitance. Reduced current slows transitions and increases delay
• Control range: Current-starved inverters typically achieve 2:1 to 5:1 delay tuning ratios. Larger ratios require extreme current reduction that compromises noise immunity and increases sensitivity to disturbances
• Delay versus control voltage: The delay-voltage characteristic is inherently nonlinear, following transistor current-voltage relationships. Linearization through biasing techniques improves controllability
• Power consumption: Current starvation increases delay at the cost of extended transition times, which can increase short-circuit power dissipation in subsequent stages
• Noise sensitivity: Reduced drive strength makes current-starved inverters more susceptible to supply noise and crosstalk during the extended transition period

Shunt-Capacitor Delay Elements

Variable capacitive loading provides an alternative delay control mechanism:

• Implementation: Varactors (voltage-variable capacitors) or switched capacitor banks at the output node change the effective load capacitance. Higher capacitance increases RC delay
• Advantages: Shunt-capacitor approaches maintain full drive strength during transitions, preserving noise immunity and minimizing supply sensitivity
• Tuning range: Varactor capacitance ratios and switched capacitor configurations determine the achievable delay range, typically similar to current-starved approaches
• Area considerations: Achieving significant delay tuning through capacitive loading requires substantial capacitor area, particularly for heavily loaded nodes
• Mixed approaches: Combining current-starving and capacitive loading extends tuning range while managing the disadvantages of each technique

Differential Delay Lines

Differential implementations provide enhanced supply rejection and common-mode noise immunity:

• Current-mode logic delay: CML delay elements use differential pairs with resistive or active loads. Tail current controls the switching speed and hence delay
• Supply rejection: Differential operation provides first-order rejection of supply variations, as supply noise affects both differential paths equally and cancels in the difference
• Interpolating delay: Differential structures enable precise delay interpolation by weighting contributions from multiple delay stages, achieving sub-gate-delay resolution
• Power considerations: CML circuits draw constant current regardless of switching activity, consuming more power than CMOS implementations at low frequencies but potentially less at very high frequencies

Delay Line Calibration

Maintaining accurate delay despite variations requires calibration mechanisms:

• Delay-locked loop calibration: A DLL servo loop adjusts the delay line control voltage to match the total delay to a reference clock period, creating a calibrated delay reference
• Replica biasing: A replica delay element within a feedback loop generates the control voltage needed to achieve a specific delay, tracking process and temperature variations
• Digital calibration: Lookup tables store correction codes determined during characterization, applying appropriate adjustments based on operating conditions
• Background calibration: Continuous calibration during normal operation maintains accuracy without interrupting primary function, essential for long-term stability

Time Amplification Techniques

Time amplifiers multiply small time differences to facilitate measurement by subsequent TDC stages. This concept parallels voltage amplification in traditional analog systems, enabling practical implementation of high-resolution time-domain processing.

Vernier-Based Time Amplification

The vernier principle inherently provides time amplification:

• Amplification mechanism: With two delay lines having delays D1 and D2 where D1 > D2, a time difference propagates through successive stages, growing by (D1-D2) per stage. The gain equals D1/(D1-D2)
• Gain limitations: Practical gain is limited by the achievable delay matching. Gains of 10-20 are common; higher gains require impractically precise matching or calibration
• Noise accumulation: Each delay stage adds its own jitter contribution. Total output jitter increases with the number of stages traversed, potentially negating resolution benefits
• Metastability concerns: When the amplified time interval approaches zero, the arbiters detecting coincidence can enter metastable states, requiring resolution time

Regenerative Time Amplifiers

Regenerative (positive feedback) structures can achieve larger time amplification factors:

• SR latch time amplifier: A cross-coupled SR latch fed with closely-spaced edges amplifies the time difference through the regeneration process. The output separation greatly exceeds the input difference
• Gain characteristics: Regenerative amplifiers provide very high gain for small input time differences but saturate for larger inputs. The gain is highly nonlinear near zero input
• Metastability window: Near zero input time difference, regeneration time becomes unbounded as the circuit approaches its metastable equilibrium point
• Two-stage approaches: Cascading a coarse amplifier with a fine regenerative stage combines the linear response of delay-based amplification with the high gain of regeneration

Gated Ring Oscillator Time Amplifiers

Gated ring oscillators provide a unique approach to time amplification:

• Operating principle: Start and stop signals enable and disable a ring oscillator. The number of oscillations during the enabled period encodes the amplified time interval
• Amplification factor: The gain equals the oscillator frequency times the measurement period. Higher frequency oscillators provide larger amplification
• Quantization: The discrete nature of oscillation counting introduces quantization error equal to one oscillation period, setting a resolution floor
• Phase preservation: Careful design preserves oscillator phase through the stop-start sequence, enabling measurements shorter than one oscillation period through phase interpolation

Successive Approximation Time Amplification

Multi-stage architectures apply time amplification successively for enhanced resolution:

• Pipeline structure: Each stage provides moderate gain while maintaining linearity, with residual time intervals passed to subsequent stages. Total gain is the product of stage gains
• Calibration requirements: Inter-stage gain and offset must be precisely controlled or calibrated. Background calibration techniques enable continuous accuracy maintenance
• Power-resolution optimization: Early stages with relaxed resolution requirements can use lower-power circuits, concentrating precision circuitry in the final interpolation stages
• Redundancy and error correction: Overlapping stage ranges with digital error correction relax matching requirements, similar to techniques used in pipelined ADCs

Phase Interpolators

Phase interpolators generate output signals with phases between those of reference signals, enabling fine timing adjustment in clock systems, serial communication links, and TDC interpolation stages.

Weighted Summation Phase Interpolation

The most common phase interpolation approach combines reference phases through weighted summation:

• Basic principle: Multiple reference phases drive parallel transconductance stages whose outputs sum into a common load. Adjusting the transconductance weights shifts the output phase continuously between reference phases
• Linearity considerations: Perfectly linear interpolation requires sinusoidal reference signals and appropriate amplitude control. Practical implementations with digital edges exhibit nonlinearity that must be characterized and corrected
• Resolution: Digital weight control provides discrete phase steps. Finer resolution requires more bits of weight control but increases complexity and power
• Quadrature reference phases: Using four reference phases at 0, 90, 180, and 270 degrees enables interpolation across the full clock period with reasonable linearity

Current-Steering Phase Interpolators

Current-steering implementations offer advantages for high-speed applications:

• CML implementation: Differential current switches steer current between loads based on reference clock phases. The interpolated output emerges as the weighted sum of phase-shifted currents
• Thermometer versus binary control: Thermometer-coded current sources provide inherently monotonic interpolation at the cost of more control lines. Binary weighting reduces complexity but can create non-monotonic steps
• Bandwidth requirements: Phase interpolator bandwidth must significantly exceed the operating frequency to avoid phase errors from limited slew rate
• Power optimization: Current-mode circuits consume constant power regardless of phase setting, creating opportunities for power reduction through current scaling at lower data rates

Delay-Based Phase Interpolation

Alternative approaches use delay adjustment rather than amplitude weighting:

• Multiplexed delay lines: Selecting among multiple delay paths through a multiplexer provides discrete phase adjustment. Interpolation between adjacent taps requires additional fine adjustment
• Continuous delay interpolation: Varying the delay of a single path through voltage-controlled elements achieves continuous phase adjustment but with nonlinear voltage-to-phase relationship
• Hybrid approaches: Combining coarse delay selection with fine weighted interpolation provides both wide range and high resolution with manageable complexity

Phase Interpolator Calibration

Achieving accurate phase interpolation requires careful calibration:

• Linearity calibration: Characterizing the actual phase versus code relationship enables digital predistortion or lookup table correction to achieve linear phase adjustment
• Gain matching: Ensuring equal weighting between interpolation branches maintains accuracy. Foreground or background calibration can measure and correct imbalances
• Reference phase calibration: Errors in the reference phases (departure from ideal 0/90/180/270 degree spacing) directly translate to interpolation errors and require compensation
• Temperature tracking: Phase interpolator characteristics vary with temperature. Periodic recalibration or temperature-compensated biasing maintains accuracy

Vernier Delay Lines

Vernier delay lines exploit precise delay differences between two delay chains to achieve sub-element timing resolution, forming the basis of high-resolution TDCs and precision timing systems.

Vernier Principle and Resolution

The vernier concept enables timing resolution finer than individual delay element precision:

• Fundamental concept: Two signals traverse delay lines with slightly different per-stage delays. The faster signal gradually catches up to the slower signal, with the catch-up rate equal to the delay difference per stage
• Resolution derivation: If the two delay lines have per-stage delays of D1 and D2, the minimum resolvable time difference equals |D1 - D2|. This can be made arbitrarily small by closely matching the delays
• Practical resolution limits: Random mismatch between delay elements sets a practical floor on achievable delay difference, typically limiting vernier resolution to a few picoseconds in advanced CMOS
• Measurement range: The total measurement range equals N times the difference delay, where N is the number of stages. Very fine resolution requires many stages for useful range

Vernier Delay Line Implementation

Practical vernier delay lines require careful attention to matching and calibration:

• Delay element design: Both delay lines typically use identical element topologies with small deliberate differences (slightly different transistor sizes, load capacitances, or supply currents) to create the desired delay offset
• Matching strategies: Common-centroid layout, matched routing, and interdigitation minimize systematic differences between corresponding stages in the two lines
• Calibration requirements: Process variations create unpredictable delay differences. Calibration determines the actual resolution and corrects for stage-to-stage variations
• Differential implementation: Using differential delay elements improves supply rejection and reduces sensitivity to common-mode disturbances

Coincidence Detection

Detecting when the two delay line signals coincide is critical to vernier operation:

• Arbiter-based detection: RS latches or specialized arbiter circuits at each tap determine which signal arrives first. The transition from "A first" to "B first" across the array identifies the coincidence point
• Metastability handling: Near the coincidence point, signal arrival times may be so close that arbiters enter metastable states. Extended resolution time and error detection improve reliability
• Bubble detection: Noise and metastability can create "bubbles" in the thermometer-coded output where isolated arbiters switch incorrectly. Digital post-processing corrects these errors
• Phase detector approaches: Continuous-time phase detectors can replace discrete arbiters, providing analog output proportional to the remaining time difference for interpolation

Looped and Recycling Vernier Architectures

Modified architectures extend range while maintaining fine resolution:

• Cyclic vernier: Connecting the delay line ends in rings allows signals to circulate multiple times. Counting complete cycles plus fractional position extends dynamic range dramatically
• Recycling architecture: Retiming and recirculating signals through the same physical delay elements reduces area while maintaining resolution
• Hierarchical approaches: Coarse measurement identifies the approximate time interval; fine vernier measurement provides sub-coarse-step resolution. This reduces the required number of vernier stages
• Noise and accuracy trade-offs: Extended measurement time in cyclic architectures accumulates additional jitter. Optimal design balances range requirements against noise accumulation

Time-Based Analog-to-Digital Converters

Time-based ADCs represent analog signals as time intervals rather than amplitude samples, enabling all-digital or nearly all-digital implementation that scales favorably with CMOS process technology.

Voltage-to-Time Conversion

The front-end of a time-based ADC converts voltage amplitude into a time interval:

• Ramp comparison: A voltage ramp starts from a reference level when triggered. The input voltage determines when the ramp crosses a threshold, encoding the input as the time to threshold crossing
• Current integration: A constant current charges a capacitor toward the input voltage. The charging time until a comparator trips encodes the input level as a time interval
• VCO-based conversion: The input voltage controls a voltage-controlled oscillator. Counting oscillator cycles during a fixed interval yields a digital output proportional to input voltage
• Delay modulation: Input voltage controls the delay through a delay line. Comparing the delayed signal to a reference produces a pulse whose width encodes the input

VCO-Based ADC Architectures

VCO-based ADCs have gained significant attention due to their inherent integration and process scaling advantages:

• Open-loop VCO ADC: The input signal modulates VCO frequency. Phase accumulation over the sampling period provides inherent first-order noise shaping, improving effective resolution
• Ring oscillator implementation: Simple ring oscillators serve as VCOs, with multiple output phases enabling higher resolution through phase quantization
• Delta-sigma operation: Placing the VCO-based quantizer within a feedback loop adds additional noise shaping orders, achieving high resolution in a narrow bandwidth
• Multi-bit quantization: Counting multiple oscillator cycles and quantizing phase provides multi-bit resolution per sample, reducing required oversampling ratio
• Linearity challenges: VCO frequency versus control voltage nonlinearity creates distortion. Calibration, predistortion, or feedback linearization addresses this limitation

Time-Domain Quantization

Converting the time-encoded signal to digital output requires TDC functionality:

• Counter-based quantization: Simple counting during the encoded time interval provides straightforward digitization but limits resolution to the reference clock period
• Interpolating quantization: Delay-line or vernier TDCs provide sub-clock-period resolution, improving effective number of bits without increasing reference frequency
• Flash TDC: Parallel sampling of a delay line provides single-shot conversion with resolution determined by the delay per stage
• SAR time-domain ADC: Successive approximation approaches use binary search in the time domain, applying test delays and comparing to find the encoded time interval

Performance Considerations

Time-based ADCs present unique performance characteristics:

• Resolution limits: Thermal noise in the voltage-to-time converter and TDC jitter ultimately limit achievable resolution. Current noise in integrators and VCO phase noise are key contributors
• Speed capabilities: Time-based architectures can achieve very high sample rates since the critical timing circuits benefit from fast transistor switching in scaled processes
• Power efficiency: Digital-intensive implementation enables aggressive voltage scaling and benefits from technology improvements, often achieving excellent power efficiency at moderate resolutions
• Area advantages: Minimal analog circuitry reduces area compared to traditional ADCs, particularly valuable in array applications such as imaging sensors
• Calibration needs: Nonlinearities in voltage-to-time conversion and TDC quantization typically require calibration for high-accuracy applications

Pulse-Width Modulation Processing

Pulse-width modulation (PWM) encodes analog information as the duty cycle of a switching waveform, enabling efficient power control, signal processing, and communication.

PWM Generation Techniques

Creating PWM signals from analog inputs involves several approaches:

• Comparator-based generation: Comparing the analog input to a triangle or sawtooth reference waveform produces a PWM output whose duty cycle is proportional to the input level
• Sigma-delta modulation: Single-bit sigma-delta modulators produce PWM-like outputs with shaped quantization noise, enabling high-resolution representation at the cost of high switching frequency
• Time-based generation: Voltage-to-time converters produce pulse widths directly proportional to input voltage without requiring analog comparators
• Digital synthesis: Digital counters and comparators generate PWM signals with duty cycles corresponding to digital input codes, common in microcontroller peripherals

Class D Amplification

PWM enables highly efficient power amplification in Class D topologies:

• Operating principle: The PWM signal drives output transistors that switch between supply rails. An output filter recovers the audio-frequency content while rejecting switching frequency components
• Efficiency advantages: Output transistors operate only in fully-on or fully-off states, minimizing power dissipation. Practical efficiencies exceed 90%, far surpassing linear amplifiers
• Modulation schemes: AD (analog PWM), BD (differential PWM), and various hybrid schemes offer different trade-offs in efficiency, common-mode rejection, and EMI characteristics
• Filter design: LC output filters must pass the audio band while attenuating switching frequency components. Filter losses reduce overall efficiency
• Feedback techniques: Closing feedback around the entire amplifier (including output filter and load) improves linearity and reduces output impedance

PWM Signal Processing

Processing operations can be performed directly on PWM-encoded signals:

• Multiplication by logic: AND-ing two PWM signals produces a signal whose average is proportional to the product of the input duty cycles, enabling analog multiplication using digital gates
• Integration: Low-pass filtering a PWM signal extracts the average value, performing integration. RC time constants determine the effective integration window
• Addition and subtraction: Appropriate logic combinations of PWM signals perform addition and subtraction operations on the encoded values
• Feedback systems: PWM signals can control processes (motor speed, temperature, power conversion) in closed-loop systems with minimal analog circuitry

PWM-to-Analog Conversion

Recovering analog signals from PWM representation requires filtering:

• Passive filtering: Simple RC or LC low-pass filters extract the average value from PWM waveforms. Filter corner frequency must be well below the switching frequency
• Active filtering: Switched-capacitor or continuous-time active filters provide sharper cutoff and controlled frequency response
• Oversampling and noise shaping: Higher switching frequencies relative to signal bandwidth improve reconstruction quality by pushing switching artifacts further from the signal band
• Digital filtering: Oversampling followed by digital low-pass filtering achieves high-quality reconstruction with minimal analog circuitry

Asynchronous Signal Processing

Asynchronous signal processing operates without a global clock, using event-driven communication between processing elements. This approach offers advantages in power consumption, electromagnetic interference, and average-case versus worst-case performance.

Asynchronous Circuit Fundamentals

Asynchronous operation requires different design approaches than synchronous systems:

• Handshaking protocols: Communication between asynchronous elements uses request-acknowledge handshaking. The sender requests data transfer; the receiver acknowledges completion before the next transfer can begin
• Delay insensitivity: Properly designed asynchronous circuits operate correctly regardless of gate and wire delays, providing inherent robustness to timing variations
• Completion detection: Circuits must detect when computation is complete rather than waiting for worst-case clock periods. Dual-rail encoding and completion detection logic address this requirement
• Hazard avoidance: Asynchronous circuits must avoid hazards (glitches) that could cause incorrect handshaking. Careful logic design using hazard-free gates ensures correct operation

Level-Crossing Sampling

Asynchronous ADCs can sample signals at level crossings rather than fixed time intervals:

• Event-driven sampling: Rather than sampling at regular clock intervals, level-crossing ADCs produce output events only when the signal crosses threshold levels. Sparse signals generate few samples
• Information efficiency: Level-crossing sampling adapts naturally to signal activity, producing more samples during rapid changes and fewer during quiescent periods
• Power proportional to activity: Power consumption scales with signal activity rather than worst-case sampling rate, offering significant energy savings for bursty signals
• Reconstruction requirements: Recovering continuous waveforms from level-crossing samples requires different algorithms than uniform sampling, typically involving interpolation between crossing events

Asynchronous Delta-Sigma Modulation

Continuous-time delta-sigma concepts adapt to asynchronous implementation:

• Asynchronous comparator operation: Rather than clocked sampling, the modulator transitions whenever the integrator output crosses threshold. Transition frequency encodes the input signal
• First-order loop behavior: Simple asynchronous delta-sigma loops provide first-order noise shaping with transition density proportional to input level
• Higher-order considerations: Extending asynchronous operation to higher-order loops requires careful stability analysis and may use hybrid synchronous-asynchronous approaches
• Reconstruction filtering: Digital decimation and filtering extract the baseband signal from the asynchronous bitstream, with effective resolution determined by oversampling ratio

Time-Mode Asynchronous Processing

Pure time-domain processing naturally aligns with asynchronous operation:

• Delay-based computation: Mathematical operations implemented through delay elements operate asynchronously, with each stage triggering the next through signal propagation
• Event timing relationships: Information encoded in relative timing between events requires no global clock reference, enabling truly asynchronous operation
• Neuromorphic connections: Time-based asynchronous processing has strong connections to neuromorphic computing, where spike timing encodes information
• Power and EMI benefits: Absence of a global clock eliminates clock power and spreads electromagnetic emissions across the spectrum, reducing peak EMI

Applications and Implementation Considerations

Time-based signal processing finds application across a wide range of systems, each with specific requirements that influence architecture selection.

Time-of-Flight Measurement

Measuring light or sound propagation time is a primary application:

• LIDAR systems: Laser pulses are emitted and their return times measured to determine target distance. Resolution of centimeters requires picosecond-class TDC performance
• 3D imaging sensors: Time-of-flight image sensors measure depth to each pixel, enabling 3D scene capture. Array implementation demands compact, power-efficient TDC architectures
• Ultrasonic ranging: Similar principles apply to ultrasonic distance measurement, though the much slower speed of sound relaxes TDC resolution requirements
• Positron emission tomography: PET scanners detect gamma ray pairs and use precise timing to localize the emission point, demanding sub-nanosecond resolution

All-Digital Phase-Locked Loops

ADPLLs replace analog loop components with digital equivalents:

• TDC-based phase detection: A TDC measures the time difference between reference and feedback clock edges, providing a digital phase error signal
• Digitally controlled oscillator: A DCO with digital frequency tuning replaces the traditional VCO, using capacitor switching or delay adjustment for frequency control
• Digital loop filter: All loop filter computations are performed digitally, enabling flexible filter design and adaptive algorithms
• Portability advantages: ADPLLs are described in HDL and synthesize across process nodes with minimal analog redesign, accelerating design migration

High-Speed Serial Links

Time-domain techniques are essential in multi-gigabit serial interfaces:

• Clock and data recovery: Phase interpolators adjust sampling clock phase to optimally sample incoming data. Timing feedback loops track transmitter frequency and phase
• Equalization: Time-domain equalization adjusts pulse response to compensate channel frequency-dependent loss, often implemented using delay-based FIR filters
• Jitter tolerance: Serial link receivers must tolerate significant timing uncertainty (jitter) in incoming data while still correctly recovering the bit sequence
• Built-in self-test: TDCs enable on-chip measurement of timing margins and jitter characteristics for production testing and system monitoring

Design Trade-offs and Optimization

Successful time-domain implementations balance multiple competing factors:

• Resolution versus power: Finer timing resolution generally requires faster circuits and more power. Architecture selection should match resolution to application needs
• Area versus accuracy: Calibration circuitry improves accuracy but consumes area. The appropriate calibration complexity depends on accuracy requirements and production volume
• Speed versus jitter: High-speed operation can accumulate more jitter through multiple processing stages. Pipeline architectures must account for jitter accumulation
• Digital versus analog partition: The optimal boundary between analog front-end and digital processing depends on the specific technology node and application requirements
• Testability: Time-domain circuits present unique test challenges. Built-in self-test capabilities and test access must be considered during design

Future Directions

Time-based signal processing continues to evolve, driven by technology trends and emerging applications:

• Advanced CMOS scaling: Sub-7nm processes offer transistors with even faster switching speeds but severely limited voltage headroom, further favoring time-domain approaches
• Machine learning acceleration: Time-domain computing architectures show promise for energy-efficient neural network inference, exploiting temporal encoding for multiply-accumulate operations
• Quantum timing: Interface circuits for quantum computing systems require precise timing control for qubit manipulation and measurement
• Neuromorphic systems: Spike-timing dependent processing in neuromorphic computers relies fundamentally on time-domain information representation and processing
• Single-photon timing: Emerging applications in quantum communication and sensing require single-photon detection with sub-100ps timing resolution
• Cryogenic time-domain circuits: Operating time-domain circuits at cryogenic temperatures for quantum computing interfaces presents unique design challenges and opportunities

Related Topics

• Specialized Analog Techniques
• Analog-to-Digital and Digital-to-Analog Conversion
• Oscillators and Signal Generators
• Analog Electronics