Electronics Guide

Gain Distribution

The total gain of a multi-stage amplifier equals the product of individual stage gains. However, the optimal distribution of gain among stages depends on several factors:

• Noise considerations: The first stage dominates overall noise performance, so it should have high gain to overcome noise contributions from subsequent stages
• Bandwidth constraints: The gain-bandwidth product limits each stage, requiring careful allocation to achieve the desired overall bandwidth
• Headroom requirements: Later stages must handle larger signal swings without clipping, potentially limiting their gain
• Stability margins: Excessive gain in any single stage may compromise stability, especially with feedback

Interstage Coupling

The method of coupling between stages affects both DC and AC performance:

• Direct coupling: Preserves DC information and extends low-frequency response to DC, but requires careful bias design and may accumulate DC offsets
• Capacitive coupling: Blocks DC offsets and simplifies biasing, but introduces low-frequency roll-off and potential phase shift
• Transformer coupling: Provides impedance transformation and DC isolation, but adds cost, size, and frequency limitations

The coupling time constant in capacitively coupled stages sets the low-frequency -3dB point. For a coupling capacitor C between a source resistance Rs and load resistance Rl, the cutoff frequency is f = 1/(2 pi C(Rs + Rl)).

DC Operating Point Design

In direct-coupled amplifiers, the DC operating points of all stages are interdependent. Design strategies include:

• Level shifting: Using diodes, zener diodes, or resistor networks to adjust DC levels between stages
• Complementary stages: Alternating NPN and PNP transistors (or N-channel and P-channel FETs) to naturally accommodate level shifts
• DC feedback: Using negative feedback around multiple stages to stabilize the overall DC operating point

Maximum Power Transfer

For maximum power transfer from source to load, the load impedance should equal the complex conjugate of the source impedance. In the purely resistive case, this means Rload = Rsource. This condition transfers 50% of the source power to the load, with the remaining 50% dissipated in the source resistance.

Matching networks can transform impedances using:

• L-networks: Two reactive elements providing a single Q value and limited bandwidth
• Pi and T networks: Three elements offering independent control of Q and transformation ratio
• Transmission line transformers: Wound or printed structures for wideband matching at RF frequencies

Voltage Transfer Optimization

For voltage amplifiers, maximum signal voltage (rather than power) transfer is often desired. This requires the load impedance to be much greater than the source impedance. In this case, nearly all the source voltage appears across the load, though power transfer is not maximized.

Practical implementations include:

• High input impedance stages: FET input stages, bootstrap circuits, or instrumentation amplifiers
• Buffer amplifiers: Unity-gain stages with high input impedance and low output impedance
• Active impedance transformation: Using feedback to modify effective input or output impedance

Noise Matching

For minimum noise figure, the source impedance should equal the optimum source impedance of the amplifier, which generally differs from both the conjugate match and the voltage transfer optimum. This noise match minimizes the combined effect of the amplifier's voltage and current noise sources.

The optimum source resistance for minimum noise is approximately Ropt = en/in, where en is the equivalent input voltage noise and in is the equivalent input current noise. Reactive components can be added to achieve the optimum complex source impedance.

Noise Sources in Amplifiers

Several distinct mechanisms contribute to amplifier noise:

• Thermal noise: Generated by random electron motion in resistors, with spectral density 4kTR V^2/Hz
• Shot noise: Arising from discrete charge carriers crossing junctions, with spectral density 2qI A^2/Hz
• Flicker (1/f) noise: Low-frequency noise with power spectral density inversely proportional to frequency, dominant in semiconductors below the corner frequency
• Burst (popcorn) noise: Random telegraph-like switching between discrete levels, caused by trapping centers

Noise Figure and Noise Factor

The noise factor F quantifies how much an amplifier degrades the signal-to-noise ratio:

F = (SNR at input) / (SNR at output)

Noise figure NF is the noise factor expressed in decibels: NF = 10 log10(F) dB. An ideal noiseless amplifier has NF = 0 dB. Practical amplifiers always add some noise, resulting in NF greater than 0 dB.

Cascaded Noise Figure

For cascaded stages, the Friis formula gives the overall noise factor:

Ftotal = F1 + (F2-1)/G1 + (F3-1)/(G1 x G2) + ...

This formula reveals that the first stage dominates overall noise performance, especially if it has high gain. Subsequent stages contribute progressively less as their noise is divided by the accumulated gain of preceding stages. This principle guides the design of low-noise amplifier chains.

Low-Noise Design Techniques

Practical strategies for minimizing amplifier noise include:

• Device selection: Choose devices with low noise voltage and current for the given source impedance
• Operating point optimization: Bias devices at currents that minimize noise for the signal bandwidth
• Source impedance matching: Transform the source to present the optimum noise impedance to the amplifier
• Bandwidth limiting: Restrict bandwidth to only what the signal requires, as noise integrates over bandwidth
• Parallel devices: Using multiple devices in parallel reduces voltage noise by the square root of the number of devices

Types of Distortion

• Harmonic distortion: Generation of frequency components at integer multiples of the input frequency, characterized by THD (Total Harmonic Distortion)
• Intermodulation distortion: Generation of sum and difference frequencies when multiple signals are present
• Crossover distortion: Occurs in push-pull stages when transitioning between devices, causing discontinuities near zero crossing
• Slew-induced distortion: Results when the amplifier cannot change output voltage fast enough to follow the input
• Thermal distortion: Caused by signal-dependent power dissipation changing device parameters during the signal cycle

Negative Feedback

Negative feedback is the primary tool for reducing distortion. By comparing output to input and correcting errors, feedback reduces distortion by a factor approximately equal to (1 + loop gain).

For an amplifier with open-loop distortion Do and loop gain T:

Closed-loop distortion = Do / (1 + T)

However, feedback introduces trade-offs:

• Reduces gain by the same factor it reduces distortion
• Can cause instability if not properly compensated
• May introduce transient intermodulation distortion if slew rate is insufficient

Feedforward Correction

Feedforward error correction subtracts the distortion generated by the main amplifier using an auxiliary path. Unlike feedback, feedforward does not affect stability and can achieve very high linearity. The technique requires:

• Precise amplitude and phase matching between paths
• A highly linear error amplifier
• Careful delay matching across frequency

Feedforward is commonly used in high-power RF amplifiers where feedback bandwidth is limited.

Predistortion

Predistortion introduces complementary nonlinearity before the amplifier to cancel its inherent distortion. The predistorter's transfer characteristic is the inverse of the amplifier's nonlinearity.

• Analog predistortion: Uses diodes or transistors to generate the inverse characteristic
• Digital predistortion (DPD): Implements the inverse function in DSP, offering adaptive capability

Class Selection and Bias Optimization

The amplifier operating class significantly affects distortion:

• Class A: Device conducts throughout the signal cycle, offering lowest distortion but lowest efficiency
• Class AB: Compromise between A and B, with small crossover region requiring careful bias
• Class B: Each device conducts for half cycle, efficient but prone to crossover distortion

Bias current in Class AB stages should be optimized to minimize crossover distortion while maintaining acceptable quiescent power dissipation.

Gain-Bandwidth Trade-offs

For most amplifier configurations, the product of gain and bandwidth is approximately constant. Reducing gain increases bandwidth proportionally. The gain-bandwidth product (GBW or ft) is a fundamental figure of merit for amplifying devices.

For a single-pole system with DC gain A0 and bandwidth f3dB:

GBW = A0 x f3dB

Shunt and Series Peaking

Inductive peaking extends bandwidth by resonating with parasitic capacitances:

• Shunt peaking: An inductor in series with the load resistor resonates with load capacitance, extending bandwidth by approximately 70%
• Series peaking: An inductor between stages isolates input and output capacitances
• T-coil peaking: A mutually coupled inductor configuration achieving bandwidth extension factors of 2 to 2.5

The optimum peaking inductor value depends on the resistance and capacitance values and the desired response flatness.

Distributed Amplification

Distributed amplifiers absorb device capacitances into artificial transmission lines, achieving bandwidths from DC to many gigahertz. Multiple devices are connected with inductors forming input and output transmission lines. Each device contributes gain while its capacitance becomes part of the line.

Key characteristics:

• Bandwidth limited primarily by transmission line cutoff
• Gain proportional to number of stages
• Flat gain and good impedance match over wide bandwidth
• Higher power consumption than lumped designs

Cascode and Current-Mode Techniques

The cascode configuration reduces Miller effect multiplication of input capacitance by isolating the input device from voltage swing:

• Common-emitter/source input stage provides transconductance
• Common-base/gate output stage provides voltage gain and isolation
• Miller capacitance is reduced by factor of (1 + gmRL)

Current-mode circuits avoid voltage-swing-related bandwidth limitations by processing signals as currents. Current conveyors and current-feedback amplifiers exploit this principle.

AGC Loop Fundamentals

An AGC system forms a feedback loop comprising:

• Variable gain amplifier (VGA): Provides signal amplification with gain controlled by a control voltage or current
• Detector: Extracts amplitude information from the signal (peak, average, or RMS)
• Loop filter: Determines attack and decay time constants, smooths detector output
• Reference: Sets the desired output level

The loop adjusts VGA gain to maintain detector output equal to the reference level.

AGC Time Constants

AGC response characteristics are crucial for proper operation:

• Attack time: How quickly gain reduces when input increases; fast attack prevents overload but may cause distortion on transients
• Decay time: How quickly gain increases when input decreases; slow decay prevents gain pumping but may cause signal loss in fades
• Hold time: Delay before gain begins to increase after input decrease

Time constants must be chosen based on signal characteristics. Audio AGC typically uses attack times of 1-10ms and decay times of 100ms-1s. RF AGC may require microsecond response.

AGC Range and Dynamic Range

The AGC range defines the span of input signal levels over which output remains constant. This is limited by:

• Minimum and maximum VGA gain
• Detector sensitivity and saturation
• Noise floor at maximum gain
• Distortion at minimum gain (maximum input)

Well-designed AGC systems achieve 60-100dB of gain range while maintaining acceptable noise and distortion.

VGA Architectures

• Multiplier-based VGA: Uses an analog multiplier with the signal and control voltage as inputs; offers linear-in-dB or linear-in-voltage gain control
• Resistive divider VGA: Varies effective feedback resistance using FETs or other variable elements
• Current-steering VGA: Splits signal current between output and ground using differential pairs; provides exponential (dB-linear) gain control
• Digitally controlled VGA: Uses switched resistor networks or attenuator stages for discrete gain steps

Gain Control Characteristics

VGAs may have linear or exponential (dB-linear) gain vs. control voltage relationships:

• Linear VGA: Gain proportional to control voltage; simpler but requires logarithmic detector for dB-linear AGC
• Exponential VGA: Gain in dB proportional to control voltage; simplifies AGC design when used with linear detector

The gain control law affects AGC loop dynamics and should be matched to the detector characteristic for optimal performance.

VGA Performance Parameters

Key specifications for VGA selection:

• Gain range: Ratio of maximum to minimum gain, typically 40-80dB
• Gain accuracy: Deviation from ideal gain law, important for measurement applications
• Bandwidth vs. gain: How bandwidth varies with gain setting
• Noise figure vs. gain: Noise typically increases at lower gain settings
• Distortion vs. gain: May vary significantly across gain range
• Gain settling time: How quickly gain stabilizes after control voltage change

Basic Differential Pair

The differential pair consists of two matched transistors with joined emitters (or sources) connected to a current source. The configuration provides:

• Differential gain: Amplification of the difference between inputs
• Common-mode rejection: Attenuation of signals appearing equally on both inputs
• High input impedance: Especially with FET implementations
• Balanced outputs: Differential output signal available between collectors/drains

Differential Gain Optimization

Differential voltage gain for a BJT pair is:

Av(diff) = gm x Rc = (Ic/Vt) x Rc

where gm is transconductance, Rc is collector resistance, Ic is collector current, and Vt is thermal voltage (approximately 26mV at room temperature).

Gain can be increased by:

• Increasing collector current (improves gm but increases power and noise)
• Increasing load resistance (limited by voltage headroom and bandwidth)
• Using active loads (current mirrors provide high effective resistance)
• Adding gain stages (cascading differential pairs)

Input Stage Configurations

Different input configurations suit different applications:

• BJT differential pair: Lower noise, higher gm per current, limited input range
• JFET differential pair: Very high input impedance, low current noise, moderate voltage noise
• MOSFET differential pair: High impedance, integrated circuit compatible, higher noise than BJT
• Composite input: Combines advantages, such as JFET input with BJT cascode

CMRR Fundamentals

CMRR is defined as the ratio of differential gain to common-mode gain:

CMRR = Ad / Acm

Expressed in decibels: CMRR(dB) = 20 log10(Ad/Acm)

Good instrumentation amplifiers achieve CMRR of 100-120dB at DC, declining at higher frequencies.

Factors Limiting CMRR

Several factors degrade common-mode rejection:

• Device mismatch: Differences in transistor parameters between the two sides of the differential pair
• Resistor mismatch: Unequal load or feedback resistors convert common-mode to differential
• Tail current source impedance: Finite impedance allows common-mode signals to modulate tail current
• Power supply rejection: Supply variations can appear as common-mode input
• Parasitic capacitance imbalance: Causes CMRR to decrease with frequency

CMRR Enhancement Techniques

• Precision resistor matching: Use matched resistor networks or laser-trimmed resistors; 0.01% matching enables greater than 80dB CMRR from resistors alone
• High-impedance current sources: Cascode current sources provide impedance greater than 10M ohms, minimizing common-mode gain
• Common-mode feedback: Active feedback loop that senses and corrects common-mode level
• Instrumentation amplifier topology: Three-op-amp configuration with matched gain resistors achieves high CMRR with gain adjustment
• Trimming and calibration: Adjust resistor values or offset to null common-mode gain
• Auto-zero techniques: Periodically measure and subtract offset and common-mode errors

Frequency-Dependent CMRR

CMRR typically decreases with frequency due to:

• Phase mismatch between signal paths
• Capacitive imbalances becoming significant
• Reduced loop gain in feedback configurations

Maintaining high-frequency CMRR requires careful layout with matched trace lengths, guard rings, and shield connections. For demanding applications, fully differential signal paths from sensor to ADC may be necessary.

Component Selection

• Transistors: Match parameters for differential pairs; consider ft, noise figure, and safe operating area
• Resistors: Use low temperature coefficient types for gain-setting; consider noise contribution of high-value resistors
• Capacitors: Select appropriate dielectric for the frequency range; avoid piezoelectric ceramics in sensitive circuits
• Integrated amplifiers: Operational amplifiers provide matched components and stable performance

Layout and Grounding

Physical implementation affects performance:

• Keep sensitive traces short and away from noisy signals
• Use ground planes to reduce inductance and shield against interference
• Match trace lengths and parasitic capacitances in differential paths
• Separate analog and digital grounds, joining at a single point
• Bypass supply pins with appropriate capacitors close to the device

Testing and Verification

Thoroughly characterize amplifier performance:

• Measure gain, bandwidth, and phase response across the frequency range
• Characterize noise spectral density and integrated noise
• Test harmonic and intermodulation distortion at various signal levels
• Verify CMRR using matched-amplitude, in-phase test signals
• Check stability with varying loads and temperatures