Electronics Guide

The Charging Process

During each half-cycle, a capacitor charges through a resistor or from a current source. For a simple RC charging circuit with initial voltage V0 and supply voltage VS, the capacitor voltage follows:

V(t) = VS - (VS - V0)e^(-t/RC)

This exponential charging continues until the voltage reaches an upper threshold (VTH+), at which point the circuit switches. For more linear operation, a constant current source can charge the capacitor, producing a true linear ramp:

V(t) = V0 + (I/C)t

Linear ramps are preferred for precision timing applications and voltage-to-frequency converters because the charging time is directly proportional to the initial conditions, independent of the exponential time constant that introduces nonlinearity in RC circuits.

The Switching Mechanism

The switching element must provide hysteresis to prevent oscillation at the threshold voltage due to noise or component tolerances. This hysteresis creates two distinct threshold levels: an upper threshold (VTH+) that triggers one transition and a lower threshold (VTH-) that triggers the return transition. The difference between these thresholds (VTH+ - VTH-) is the hysteresis window or deadband.

Common switching mechanisms include:

• Schmitt triggers: Comparators or inverters with built-in hysteresis that provide clean digital-level switching
• Regenerative comparators: Circuits using positive feedback to create snap-action switching behavior
• Negative resistance devices: Components like tunnel diodes, unijunction transistors, or neon lamps that exhibit a region of negative differential resistance
• Thyristors and SCRs: Four-layer devices that latch when triggered and require current reduction to reset

Period and Frequency Determination

The oscillation period depends on the time required for the capacitor to charge between the two threshold levels. For an exponential RC charging circuit:

T = RC × ln[(VS - VTH-)/(VS - VTH+)]

For a linear current-source charging circuit:

T = C × (VTH+ - VTH-) / I

The linear relationship in current-source circuits makes them ideal for voltage-controlled oscillators where frequency must be proportional to a control voltage, and for precision timing where temperature and voltage variations in threshold levels directly translate to timing errors.

Transistor-Based Astable Multivibrator

The classic cross-coupled transistor multivibrator uses two transistors with their collectors coupled to the opposite bases through timing capacitors. When one transistor conducts, its collector voltage drops, turning off the opposite transistor through the coupling capacitor. The timing capacitor then charges through a base resistor until the opposite transistor can conduct, whereupon the cycle reverses.

Key characteristics of the transistor astable multivibrator include:

• Simple construction: Requires only two transistors, two capacitors, and four resistors for basic operation
• Wide frequency range: Can operate from sub-hertz to several megahertz depending on component selection
• Adjustable duty cycle: Asymmetric timing components produce unequal high and low times
• Temperature sensitivity: Base-emitter voltage variations affect timing accuracy
• Output waveform: Produces rectangular waves with relatively slow rise and fall times

The half-period for each transistor being off is approximately:

T1 = 0.693 × R1 × C1
T2 = 0.693 × R2 × C2

where R1 and C1 control the time transistor Q1 remains off, and R2 and C2 control the off-time of Q2. The total period is T = T1 + T2, and the duty cycle can be adjusted by varying the RC products.

Op-Amp Astable Multivibrator

An operational amplifier with positive feedback can create an astable multivibrator with more predictable behavior than discrete transistor versions. The positive feedback network establishes the threshold voltages, while a capacitor charges and discharges through a timing resistor.

In the basic configuration, a resistive divider from the op-amp output to the non-inverting input sets the threshold levels, while a capacitor connected to the inverting input integrates the output voltage. When the capacitor voltage crosses the threshold, the output switches polarity, and the charging direction reverses.

The oscillation frequency is given by:

f = 1 / (2RC × ln(1 + 2R1/R2))

where R1 and R2 form the positive feedback divider, R is the timing resistor, and C is the timing capacitor. For the common case of R1 = R2 (which gives approximately one-third and two-thirds supply voltage thresholds):

f = 1 / (2.2RC)

Advantages of the op-amp astable include better output amplitude (full rail-to-rail swing with appropriate op-amp selection), more precise threshold voltages, and easier frequency adjustment through a single timing resistor.

CMOS and Logic Gate Oscillators

Digital logic gates with high input impedance, such as CMOS inverters and Schmitt trigger gates, can form simple and reliable astable oscillators. These circuits take advantage of the built-in threshold voltage of the gates and their ability to drive capacitive loads.

A simple ring oscillator uses an odd number of inverters connected in series, with the output of the last stage feeding back to the input of the first. The oscillation frequency depends on the propagation delay of each gate:

f = 1 / (2n × tpd)

where n is the number of stages and tpd is the propagation delay per stage. While simple, ring oscillators have frequency that varies strongly with supply voltage and temperature.

More stable CMOS oscillators use an external RC network with Schmitt trigger gates. The capacitor charges and discharges between the upper and lower trigger thresholds, producing a square wave output with frequency:

f = 1 / (1.2RC)

for typical Schmitt trigger hysteresis levels. The exact coefficient depends on the specific IC family and its threshold characteristics.

Integrator-Comparator Triangle Generator

The most common triangle wave generator combines an op-amp integrator with a Schmitt trigger comparator. The integrator converts the square wave output of the comparator into a linear ramp, while the Schmitt trigger switches when the integrator output reaches the upper or lower threshold.

Circuit operation proceeds as follows:

1. When the comparator output is high, the integrator ramps downward at a rate determined by the input current and integration capacitor
2. When the integrator output reaches the lower threshold, the comparator switches to its low output state
3. With the comparator output low, the integrator ramps upward
4. When the upper threshold is reached, the comparator switches high, and the cycle repeats

The triangle wave amplitude is set by the Schmitt trigger hysteresis, and the frequency is determined by:

f = R2 / (4 × R1 × R3 × C)

where R2 and R3 form the comparator threshold divider, R1 is the integrator input resistor, and C is the integration capacitor. The peak-to-peak triangle amplitude equals the hysteresis voltage of the Schmitt trigger.

Sawtooth Wave Generation

A sawtooth wave has a linear ramp in one direction followed by a rapid reset, creating an asymmetric triangular shape. This waveform is used in CRT deflection circuits, some types of oscillators, and wherever a linear sweep with fast retrace is required.

Sawtooth generators typically use a constant current source to linearly charge a capacitor, with a fast discharge path activated when the voltage reaches an upper threshold. The reset can be implemented with:

• Transistor switch: A transistor shorts the timing capacitor when triggered by a comparator
• SCR or thyristor: Latches on at the threshold voltage and conducts until capacitor voltage falls below holding current
• Programmable unijunction transistor: Fires at a programmable threshold and resets the capacitor through negative resistance action

The frequency of a sawtooth generator is approximately:

f = I / (C × VP)

where I is the charging current, C is the timing capacitor, and VP is the peak sawtooth voltage. This assumes the reset time is negligible compared to the ramp time.

Precision Ramp Generators

For applications requiring highly linear ramps with accurate slopes, precision ramp generators use temperature-compensated current sources and high-quality capacitors. Key considerations include:

• Current source stability: Reference voltage and resistor temperature coefficients directly affect ramp linearity
• Capacitor selection: Polypropylene or polystyrene capacitors offer the best linearity; ceramic capacitors exhibit voltage-dependent capacitance
• Op-amp selection: Input bias current causes ramp error; use FET-input or auto-zero amplifiers for best results
• Reset switch characteristics: Charge injection from the reset switch creates an initial voltage step that affects low-amplitude operation

Precision ramp generators often include trimming provisions for adjusting the ramp slope and reset level to compensate for component tolerances and achieve the required accuracy.

Charge-Balance VFC Architecture

The charge-balance VFC is the most accurate topology, maintaining excellent linearity over a wide dynamic range. It operates on the principle that the average current into an integrating capacitor must be zero over time for the circuit to remain in equilibrium.

In operation:

1. The input voltage creates a proportional current that charges the timing capacitor
2. When the capacitor voltage reaches a threshold, a comparator triggers a precision one-shot that injects a fixed charge packet in the opposite direction
3. The one-shot output provides the frequency output, with each pulse representing a fixed amount of charge
4. At equilibrium, the number of charge packets per second exactly balances the input current

The output frequency is:

f = VIN / (R × Q)

where VIN is the input voltage, R is the input resistor that converts voltage to current, and Q is the charge per output pulse. The linearity depends on the precision of the charge packets and the stability of the input resistor.

Charge-balance VFCs can achieve linearity better than 0.01% and dynamic ranges exceeding 10,000:1, making them suitable for precision data acquisition, isolated signal transmission, and integrating measurements.

Multivibrator-Based VFC

Simpler VFCs use the input voltage to control the charging current in a standard relaxation oscillator. While less accurate than charge-balance designs, these circuits offer lower cost and simpler implementation for applications where moderate linearity is acceptable.

The input voltage typically controls either:

• Timing current: A transconductance stage converts input voltage to a proportional current that charges the timing capacitor
• Timing resistance: A voltage-controlled resistor (such as a FET operating in the linear region) modulates the RC time constant
• Threshold voltage: The comparator threshold varies with input voltage, changing the capacitor swing required per cycle

These simpler architectures typically achieve 0.1% to 1% linearity, suitable for analog-to-digital conversion in measurement systems, motor speed control, and frequency-shift keying modulation.

VFC Applications

Voltage-to-frequency converters find use in numerous applications:

• Isolated signal transmission: Optical isolators can transmit frequency-encoded signals across isolation barriers without affecting accuracy
• Integrating analog-to-digital conversion: Counting VFC pulses over a fixed time integrates the input signal, providing inherent noise rejection
• Long-distance signal transmission: Frequency-encoded signals are immune to cable resistance and thermoelectric effects that degrade DC signals
• Ratiometric measurements: Dual VFCs with a common reference can make ratio measurements independent of component drift
• Frequency-shift keying: VFCs can generate FSK modulation for data transmission

Basic CCO Operation

The simplest CCO uses the input current directly to charge a timing capacitor. When the capacitor voltage reaches a threshold, a discharge mechanism resets the capacitor, and the cycle repeats. Since the charging time is inversely proportional to the current (T = C*V/I), the frequency is directly proportional to the input current:

f = I / (C × VTH)

where I is the input current, C is the timing capacitor, and VTH is the voltage swing per cycle.

This linear relationship between frequency and current makes CCOs inherently more linear than voltage-controlled oscillators based on exponential RC charging, where frequency depends on the logarithm of a voltage ratio.

Emitter-Coupled CCO

An emitter-coupled multivibrator provides excellent current-to-frequency conversion. The input current sets the tail current of a differential pair, which alternately charges and discharges a timing capacitor through the collector loads. The switching occurs when the capacitor voltage shifts the differential pair to the opposite state.

Advantages of the emitter-coupled CCO include:

• Wide dynamic range: Can operate over three or more decades of input current
• Good linearity: Direct current-to-frequency relationship without exponential terms
• Differential outputs: Produces complementary square wave outputs
• High frequency capability: Can operate into the hundreds of megahertz with appropriate transistors

The output frequency is approximately:

f = I / (4 × C × VBE)

where I is the input current, C is the timing capacitor, and VBE is the base-emitter voltage (approximately 0.6V to 0.7V). Temperature compensation is required for precision applications due to the VBE temperature coefficient.

Applications of Current-Controlled Oscillators

CCOs are essential in many circuit topologies:

• Phase-locked loops: Current-steering CCOs provide wide tuning range and good phase noise in PLL voltage-controlled oscillators
• Current-to-frequency conversion: Photodiode and sensor outputs often produce currents that are more conveniently processed as frequencies
• Logarithmic frequency control: When preceded by a voltage-to-current converter with logarithmic characteristic, CCOs provide musical octave scaling
• Analog computation: CCOs can perform multiplication and division when the timing capacitor is also current-controlled

555 Timer Architecture

The 555 timer contains two comparators, an RS flip-flop, a discharge transistor, and a resistive voltage divider that establishes internal threshold levels at one-third and two-thirds of the supply voltage. This architecture enables both monostable (one-shot) and astable (free-running) operation with minimal external components.

Key internal blocks include:

• Threshold comparator: Triggers when the external capacitor voltage exceeds 2/3 VCC
• Trigger comparator: Sets the flip-flop when the trigger input falls below 1/3 VCC
• RS flip-flop: Stores the oscillator state and controls the discharge transistor
• Discharge transistor: Provides a low-impedance path to discharge the timing capacitor
• Output stage: Sources and sinks up to 200mA for driving loads directly

Astable Mode Operation

In astable mode, the 555 produces a continuous rectangular wave output. The timing capacitor charges through two resistors (RA and RB) connected in series and discharges through only RB, creating an asymmetric charge/discharge cycle that determines the duty cycle.

The output high time is:

T_HIGH = 0.693 × (RA + RB) × C

The output low time is:

T_LOW = 0.693 × RB × C

The total period and frequency are:

T = 0.693 × (RA + 2RB) × C
f = 1.44 / [(RA + 2RB) × C]

The duty cycle is inherently greater than 50% in the standard configuration because the capacitor charges through both RA and RB but discharges through only RB. For duty cycles below 50%, a diode can bypass RA during charging, or alternative configurations using the 555 control voltage input can be employed.

CMOS Timer Variants

CMOS versions of the 555 timer, such as the ICM7555 and TLC555, offer improved performance for many applications:

• Lower power consumption: Quiescent current reduced from milliamps to microamps
• Wide supply voltage range: Operates from 2V to 15V or higher
• Higher input impedance: Reduces timing errors from input current
• Cleaner output transitions: Reduced ground bounce and supply spikes
• Improved timing accuracy: More symmetrical threshold voltages

The trade-off is reduced output current capability, typically 10-20mA versus 200mA for the bipolar 555, requiring buffer transistors for high-current loads.

Precision Timer Applications

For applications requiring better accuracy than the standard 555, several approaches can improve timing precision:

• External voltage reference: The 555 control voltage input allows substitution of an external reference for the internal 2/3 VCC threshold
• Temperature compensation: Thermistors or temperature-sensing ICs can adjust timing components to compensate for drift
• Crystal control: For precise frequency applications, the 555 can be synchronized to a crystal oscillator
• Dual-timer ICs: Devices like the 556 (dual 555) enable more complex timing functions with matched characteristics

PUT Structure and Operation

The PUT is structurally similar to a thyristor, with anode, cathode, and gate terminals. However, it is specifically designed to exhibit a negative resistance characteristic that makes it ideal for relaxation oscillator applications.

Operating regions include:

• Off state: With anode voltage below the gate voltage plus a diode drop, the PUT blocks current and the anode-cathode path presents high impedance
• Negative resistance region: When the anode voltage exceeds the gate voltage by approximately 0.6V, the device triggers and transitions toward the on state
• On state: Once triggered, the PUT exhibits low impedance (similar to a forward-biased diode) until the anode current falls below the holding current

The peak-point voltage (VP) at which triggering occurs is:

VP = VG + VD

where VG is the gate voltage and VD is approximately 0.6V (the forward voltage of the internal junction). Since VG is externally programmable through a voltage divider, the trigger threshold can be set to any desired value.

PUT Relaxation Oscillator

The basic PUT oscillator consists of a timing capacitor, a charging resistor, the PUT, a gate bias network, and a load resistor in the cathode circuit for output coupling.

Circuit operation follows this sequence:

1. The timing capacitor charges through the charging resistor toward the supply voltage
2. When the capacitor voltage reaches VP, the PUT fires and rapidly discharges the capacitor through the low on-state resistance
3. As the capacitor discharges, the anode current decreases; when it falls below the valley current, the PUT turns off
4. The capacitor begins charging again, and the cycle repeats

The oscillation frequency is approximately:

f = 1 / [RC × ln(VCC / (VCC - VP))]

The output pulse appears across the cathode resistor and has amplitude determined by the discharge current and resistor value.

PUT Design Considerations

Successful PUT oscillator design requires attention to several parameters:

• Gate circuit impedance: Too low an impedance prevents the gate-cathode junction from forward biasing during firing; too high allows excessive gate current variation
• Charging resistor limits: Must be large enough to limit current below the holding current for reliable turn-off, yet small enough for proper capacitor charging
• Valley current matching: The minimum current through the device must exceed the valley current for reliable oscillation
• Temperature effects: Both the intrinsic offset voltage and the gate divider affect temperature stability

PUTs are available in standard transistor packages and are commonly used in phase-angle controllers, motor speed controls, and low-cost timing circuits where their simplicity and reliability are advantageous.

Switched Capacitor Oscillator Principle

In a switched capacitor circuit, a capacitor is alternately connected between an input voltage and an output node by complementary switches operating at a clock frequency. The average current transferred equals the charge moved per cycle times the clock frequency:

I_AVG = C × V × fCLK

This creates an equivalent resistance of:

R_EQ = 1 / (C × fCLK)

When this equivalent resistance sets the timing in a relaxation oscillator, the oscillation frequency becomes proportional to the clock frequency and largely independent of absolute capacitor values, depending instead on capacitor ratios which are well controlled in IC processes.

Integrated Circuit Implementation

Charge pump oscillators are widely used in integrated circuits for several reasons:

• No external components: The oscillator can be fully integrated without precision external resistors or capacitors
• Frequency stability: When referenced to a crystal oscillator clock, the output frequency tracks the crystal accuracy
• Process independence: The frequency depends on ratios, not absolute values, reducing sensitivity to process variations
• Voltage control: The control voltage can set the charge transferred per cycle for VCO applications

Applications include reference oscillators in microcontrollers, clock generators in data acquisition systems, and VCOs in phase-locked loops.

Charge Pump Phase-Locked Loops

While not strictly an oscillator, the charge pump is essential to modern phase-locked loop design. The phase detector output controls switches that inject or remove charge from a loop filter capacitor, creating a voltage that controls the VCO frequency. This topology provides:

• Zero static phase error: The loop drives phase error to zero, not to a finite value as with analog multiplier phase detectors
• Wide capture range: Frequency detector action extends capture range beyond the narrow band of phase-only detection
• Digital compatibility: The phase-frequency detector and charge pump interface directly with digital dividers and control logic

Burst Mode Principle

In burst mode, the oscillator alternates between two states:

• Active burst: The oscillator runs at its normal, relatively high frequency for a number of cycles
• Idle period: The oscillator stops and enters a low-power sleep state

The effective average frequency is:

f_AVG = f_OSC × T_BURST / (T_BURST + T_IDLE)

where f_OSC is the oscillator frequency during active bursts, T_BURST is the burst duration, and T_IDLE is the idle period.

Advantages of Burst Mode

Burst mode offers several benefits over continuous low-frequency operation:

• Improved noise performance: The oscillator operates in a frequency range where timing jitter and phase noise are lower
• Better timing accuracy: High-frequency oscillators have smaller proportional timing errors than very low-frequency circuits
• Reduced power consumption: The idle periods allow significant power savings in battery-operated devices
• Component size reduction: Higher operating frequencies require smaller timing capacitors
• EMI spectrum spreading: The burst pattern spreads emissions over a wider bandwidth, reducing peak spectral density

Burst Mode Applications

Common applications of burst mode include:

• Switching power supplies: At light loads, burst mode reduces switching losses while maintaining output regulation
• Piezoelectric transducer drivers: Burst operation matches the mechanical response of the transducer
• Low-power wireless sensors: Periodic wake-up oscillators use burst mode for minimum average power
• Light dimmers and motor controllers: Burst firing provides smooth control at low output levels

Design Considerations

Implementing burst mode requires attention to:

• Startup time: The oscillator must reach stable operation quickly at the start of each burst
• Shutdown transients: Clean shutdown avoids ringing or partial cycles that affect accuracy
• State retention: Any analog state (such as integrator voltage) must be preserved or reset appropriately
• Burst timing control: Accurate counting of cycles or timing of bursts is essential for predictable average output
• Audible noise: In power applications, burst frequencies in the audio range (20Hz-20kHz) may create objectionable acoustic noise

Component Selection

Timing component selection significantly impacts oscillator performance:

• Timing capacitors: Film capacitors (polypropylene, polystyrene) offer best stability; ceramic capacitors exhibit voltage and temperature dependence that degrades timing accuracy; electrolytic capacitors are unsuitable for precision timing due to high leakage and variability
• Timing resistors: Metal film resistors provide good temperature stability; thick film resistors may exhibit voltage coefficients; carbon composition resistors have relatively poor stability
• Current sources: For precision applications, reference-derived current sources provide better stability than simple resistor-based charging
• Comparators and op-amps: Input bias current and offset voltage affect threshold accuracy; input offset temperature drift is often the dominant error source

Temperature Stability

Temperature affects relaxation oscillators through multiple mechanisms:

• RC time constant variation: Resistor and capacitor temperature coefficients combine to create frequency drift
• Threshold voltage changes: Comparator offset and semiconductor junction voltages vary with temperature
• Reference voltage drift: If thresholds are referenced to a voltage source, its temperature coefficient contributes to timing errors
• Leakage current changes: Semiconductor leakage currents double approximately every 10 degrees Celsius, affecting timing at high impedance nodes

Temperature compensation techniques include:

• Using components with opposing temperature coefficients that cancel
• Including thermistors in the timing network for deliberate compensation
• Referencing to temperature-compensated voltage sources
• Using digital calibration with temperature sensing

Noise and Interference Immunity

Relaxation oscillators can be susceptible to noise because the switching occurs at a specific threshold voltage that noise can falsely trigger:

• Hysteresis: Adequate hysteresis in the switching element prevents noise-induced false triggering
• Filtering: Capacitive filtering on reference and threshold voltages reduces high-frequency noise
• Layout: Keep timing components close to the switching element, minimize high-impedance trace lengths, and shield sensitive nodes from digital switching noise
• Power supply decoupling: Local decoupling capacitors prevent supply transients from coupling into the timing circuit

Output Interfacing

The oscillator output must be properly buffered and conditioned for the load:

• Buffering: Isolate the timing circuit from load variations that could affect frequency
• Level shifting: Convert oscillator output levels to match the requirements of driven circuits (TTL, CMOS, ECL, etc.)
• Edge shaping: If required, sharpen slow edges with Schmitt trigger buffers to reduce timing uncertainty
• Frequency division: For duty cycle adjustment or lower frequencies, follow the oscillator with dividers

Timing and Control

• Clock generation: Provide timing references for digital systems, microcontrollers, and sequential logic
• PWM generation: Create variable duty cycle waveforms for motor control, power conversion, and dimming
• Watchdog timers: Monitor system operation and trigger reset if software fails to respond
• Timeout circuits: Generate delays for sequential operations, debouncing, and event detection

Signal Generation and Processing

• Function generators: Produce calibrated waveforms for testing and measurement
• Sweep generators: Create linear frequency sweeps for spectrum analyzers and frequency response testing
• Ramp generators: Provide timing ramps for CRT displays, sample-and-hold circuits, and ADCs
• Tone generators: Create audio frequencies for alarms, alerts, and simple music synthesis

Power Electronics

• Switching power supplies: Control the switching frequency and duty cycle of DC-DC converters
• Motor drives: Generate PWM signals for DC motor speed control and stepper motor sequencing
• Lamp dimmers: Control AC phase angle or burst firing for incandescent and LED dimming
• Inverters: Provide timing for DC-to-AC conversion in UPS systems and solar inverters

Communication Systems

• Data encoding: Generate carrier frequencies for infrared remotes and RFID tags
• Frequency-shift keying: VCOs modulated by digital data for FSK transmission
• Clock recovery: Phase-locked loops using relaxation VCOs for bit synchronization
• Spread spectrum: Generate pseudo-noise sequences for secure communication