Electronics Guide

One Pass Around the Loop

A loop that mixes continuous and sampled signals is a sampled-data system. In a typical controller, this sequence repeats every sampling period T:

1. A timer starts the ADC at the sampling instant kT, behind an analog filter that limits the bandwidth of the measured signal.
2. Firmware scales the ADC's integer result to engineering units or to a fixed-point format.
3. The processor evaluates the control law, a difference equation in the new sample and in stored past samples and outputs.
4. It limits the result to the actuator's range and writes it to the DAC or to the PWM compare register.
5. The DAC or modulator applies the new value at its next update instant and holds it until the one after.
6. The processor updates its stored states and waits for the next sampling instant.

In Feedback Systems (second edition, chapter 11), Karl Johan Åström and Richard Murray recommend sending the output as soon as it is computed and updating the controller states afterward, which minimizes latency.

Continuous Plant, Discrete Controller

The controller sees only samples of the plant's continuous output, and the actuator delivers a staircase from a DAC or a pulse train from a PWM. Viewed from the controller, hold, plant, and sampler form a discrete-time system. Its zero-order-hold equivalent, described later, predicts a linear plant's output at the sampling instants, exactly behind an ideal hold and approximately behind a PWM. It says nothing about behavior between samples: a loop can look well damped at the sampling instants while the plant rings between them, so designers also simulate the continuous plant with the discrete controller.

The Zero-Order Hold

A zero-order hold keeps each command constant for one period. Its impulse response is a rectangular pulse of length T, so its transfer function is

G_h(s) = (1 − e^−sT)/s

and its frequency response is

G_h(jω) = T e^−jωT/2 sin(ωT/2)/(ωT/2)

The factor T cancels the 1/T that ideal sampling introduces, so the sampler and hold together have unity gain at DC. The exponential is a pure delay of T/2: a staircase lags the smooth signal it follows by half a step. At the crossover frequency ω_c, the hold therefore costs ω_cT/2 radians of phase, or 180° × f_c/f_s, while the sine ratio lowers the gain slightly.

Computation Delay

Many controllers sample at kT and apply the result at the next update instant, (k + 1)T, which fixes the output timing however long the code takes, provided it finishes within the period. That schedule adds a whole sample of delay, z⁻¹, which costs another ω_cT radians at crossover. Together, the hold and the computation delay amount to 1.5T, and their phase cost at crossover is

φ_delay = 1.5ω_cT radians = 540° × f_c/f_s

Updating the output as soon as the calculation ends cuts the added delay to the computation time but lets the update instant move with the execution time. Alternatively, the sampling instant can move later in the period, so that the calculation ends just before the modulator loads the new value.

Delay in a Pulse-Width Modulator

A PWM produces pulses rather than a staircase. A small change in duty cycle adds or removes a sliver of pulse at whichever edge the modulator moves, and the loop sees the change at that edge. For a modulator that takes one new duty value per period, with D the steady-state duty cycle, the small-signal delays measured from the start of the period in which the value takes effect are these:

A controller that samples at the start of each period and loads its result at the start of the next therefore has a total delay of (1 + D)T with trailing-edge modulation and 1.5T with symmetric modulation.

Transport Delay and Other Lags

The plant may add transport delay of its own, as when fluid travels down a pipe to a sensor. Sensor and anti-aliasing filters add lag, the decimation filter of a delta-sigma ADC adds delay, and a networked sensor or actuator adds communication latency. A pure delay τ_d costs ω_cτ_d radians at crossover and, unlike a pole, keeps adding phase without limit as frequency rises. At a 1 kHz crossover, each 100 µs of delay costs 36°.

The Sampling Theorem Is Only a Floor

The sampling theorem requires a sample rate above twice the highest frequency the loop must represent, but a controller sampled near that limit performs poorly. At f_s = 5f_c, the hold and one sample of computation delay consume 108° at crossover, more than most loops have to give. Phase, noise, and resolution set the sample rate long before the theorem does.

A Rule of Thumb from the Phase Budget

Decide how much phase margin the loop can give up to delay, φ_allowed, and solve for the sample rate, with the delay N_d counted in samples:

f_s ≥ N_d × 360° × f_c/φ_allowed

With a 1.5-sample delay, allowing 30° gives f_s ≥ 18f_c, and allowing 20° gives f_s ≥ 27f_c. A controller that updates within the same period, adding little beyond the hold, loses only 15° at f_s = 12f_c. These are rules of thumb: a direct digital design that models the delay exactly can work at lower ratios, and a plant with little phase to spare needs higher ones.

Costs of Sampling Faster

Faster sampling has costs even when the processor can keep up:

• Poles crowd toward z = 1, so coefficients need more bits. A pole with a 2 ms time constant sits at z = 0.95123 at 10 kHz, where rounding its coefficient to 8 fractional bits lengthens the time constant by 4.1 percent. At 100 kHz it sits at 0.99501, and the same rounding lengthens the time constant by 28 percent.
• The integral gain per sample, K_iT, shrinks in proportion to T, so the integrator needs more fractional bits to accumulate small errors.
• A derivative computed as the difference of successive samples amplifies measurement noise in proportion to 1/T.

Nested loops therefore often run at different rates, with the inner current loop at the PWM frequency and outer loops slower.

Aliases Become Disturbances

Any component of the measured signal above f_s/2 folds to a lower frequency. In a feedback loop the controller acts on the alias, driving the actuator at a frequency that was never present in the plant. Switching ripple is the usual source in power electronics: ripple at exactly f_s aliases to DC and shifts the regulated value, and ripple slightly away from f_s aliases to a slow beat that the loop tries to cancel.

The Filter Competes with the Loop for Phase

An anti-aliasing filter must attenuate near and above f_s/2 while adding little phase at crossover, and when f_s is only 10 to 30 times f_c, those demands conflict. With its corner at 5f_c, a first-order filter costs 11.3° at crossover and a second-order Butterworth filter costs 16.4°. If f_s = 20f_c, then f_s/2 lies only a factor of two above that corner, where the two filters attenuate by just 7.0 dB and 12.3 dB. Moving the corner to 10f_c halves the first-order filter's phase cost, to 5.7°, but leaves only 3 dB of attenuation at f_s/2. The filter therefore belongs in the loop model and in the phase budget.

Sampling Synchronized to the Switching

Converters and drives usually sidestep the conflict by timing samples to the PWM. In steady state, an inductor's triangular ripple current passes through its average value at the midpoint of each on-interval and each off-interval. With a symmetric carrier, those midpoints fall at the carrier's peaks and valleys, so a sample taken there reads the average current, away from the ringing that follows each switching edge. The method is exact only for triangular ripple in steady state; with rounded ripple, such as a capacitor voltage, a fixed sampling instant regulates the sampled value rather than the average, leaving a small offset. Averaging several samples per period also works, at the cost of the average's own delay, (M − 1)/2 fast sampling periods for an M-point average.

Design by Emulation

Emulation designs in continuous time and converts the result, reusing s-domain tools and existing analog designs. It works well when the sample rate is high compared with crossover. The procedure is:

1. Model the plant in continuous time, with the loop delay, e^−1.5sT or whatever the timing analysis gives, in the loop gain.
2. Design C(s) for the required crossover frequency and phase margin with that delay in place.
3. Convert C(s) to C(z) by one of the methods below, prewarping at crossover if Tustin's method is used.
4. Check stability and margins with an exact discrete model: the zero-order-hold equivalent of the plant, z⁻¹ for the computation delay, and C(z).
5. Simulate the continuous plant with the discrete controller, including saturation and quantization.

Direct Digital Design

Direct digital design works on the zero-order-hold equivalent of the plant, with whole-sample delays included as powers of z⁻¹. The designer can place closed-loop poles directly, shape the loop with a root locus drawn in the z-plane, map the problem into the w-plane with w = (2/T)(z − 1)/(z + 1) to use frequency-response methods, or discretize a state-space model and design state feedback. Because the model contains the sampling and the delay exactly, the design stays accurate at low ratios of sample rate to bandwidth, and it permits controllers with no continuous counterpart, such as deadbeat control.

Forward Euler

s = (z − 1)/T

The forward difference approximates a derivative by (x[k + 1] − x[k])/T, which amounts to rectangular integration with the older sample. The substitution maps z = 1 + sT, so the left half of the s-plane lands on the half-plane left of z = 1, most of which lies outside the unit circle. Only poles within the circle of radius 1/T centered at s = −1/T map inside. A stable real pole at s = −a becomes z = 1 − aT, which leaves the unit circle once aT > 2, that is, once the pole frequency exceeds f_s/π. At f_s = 20 kHz, a real pole at 5 kHz maps to z = −0.571, a stable mode that alternates in sign every sample, and a real pole at 7 kHz maps to z = −1.199, which is unstable.

Backward Euler

s = (z − 1)/(Tz)

The backward difference uses the newer sample. The substitution maps z = 1/(1 − sT), which carries the whole left half-plane into the circle of radius 1/2 centered at z = 1/2, so every stable C(s) yields a stable C(z). The error runs the other way: part of the right half-plane also lands inside the unit circle, so an unstable pole far enough to the right becomes a stable discrete pole. The pole at s = +3/T, for example, maps to z = −0.5. Used to discretize a plant model, the method can therefore hide an instability.

Tustin's Method and Prewarping

s = (2/T)(z − 1)/(z + 1)

This substitution, the bilinear transform defined in Z-Transform, is trapezoidal integration. It carries the name of Arnold Tustin, whose paper on analyzing linear systems in terms of time series appeared in Part IIA of the Journal of the Institution of Electrical Engineers in May 1947. It maps the left half-plane exactly onto the interior of the unit circle and the imaginary axis once around the circle, so stability is preserved in both directions and nothing aliases. The price is frequency warping: an analog frequency ω_a and the digital frequency ω_d where it lands satisfy ω_a = (2/T) tan(ω_dT/2). At f_s = 20 kHz, the digital response at 1, 5, and 8 kHz reproduces the analog response at 1.008, 6.37, and 19.6 kHz.

Prewarping replaces the constant 2/T with ω₁/tan(ω₁T/2):

s = [ω₁/tan(ω₁T/2)](z − 1)/(z + 1)

At z = e^jω₁T, the right side equals jω₁ exactly, so C(z) matches C(s) in both gain and phase at ω₁. Loop compensators are usually prewarped at crossover, and notch filters at their center frequency. At typical ratios the warping is small: at f_s = 20f_c, the unwarped method matches the analog response of a frequency only 0.83 percent above f_c.

Matched Pole-Zero Mapping

This method maps each pole and each finite zero of C(s) through z = e^sT, so a pole at s = −a moves to z = e^−aT. Zeros at infinity, which C(s) has whenever it has more poles than zeros, go to z = −1, so the digital version fully attenuates f_s/2, as the analog one does at infinite frequency. A common variant omits one of them so that the output depends only on earlier samples, freeing a full period for computation. The gain is set to match C(s) at DC, or at a chosen frequency when C(s) has a pole at the origin. Because the poles follow the exact sampling map, a stable pole stays stable at any sample rate, but the frequency response matches only approximately.

Zero-Order-Hold Equivalent

The zero-order-hold equivalent, also called the step-invariant transform, answers a different question: which discrete system describes a continuous one that is driven through a hold and sampled? The answer is

G(z) = (1 − z⁻¹) Z{G(s)/s}

where Z{G(s)/s} is the z-transform of the sampled step response of G(s), so the discrete step response matches the sampled continuous one exactly. For a first-order plant K/(τs + 1), the result is G(z) = K(1 − a)/(z − a), with a = e^−T/τ.

The poles map through z = e^sT, but the zeros do not map simply, and sampling can create new ones. Karl Johan Åström, Per Hagander, and Jan Sternby showed in Automatica in 1984 that as the sampling period shrinks, these sampling zeros approach limits set only by the pole excess, the denominator degree minus the numerator degree. A pole excess of two gives a limit at z = −1; a pole excess of three or more puts at least one limit outside the unit circle, so such a plant sampled fast enough has a zero outside it. The equivalent of 1/s³ has zeros at −2 ± √3, about −3.73 and −0.27, and 1/(s + 1)³ sampled every 10 ms has zeros at −3.70 and −0.27. Canceling the outer zero would take an unstable controller pole, so designs that invert the plant, deadbeat control among them, must leave such zeros in place.

Comparing the Methods

The lead compensator C(s) = (1 + s/ω_z)/(1 + s/ω_p), with its zero at 1 kHz and its pole at 5 kHz, provides its greatest phase lead, 41.8°, at the geometric mean of the two, 2.24 kHz. The table compares its discrete versions at f_s = 20 kHz, a deliberately low rate that makes the differences visible.

Both Tustin versions keep the full lead, and prewarping also matches the gain. The negative pole of forward Euler adds 15.5° of spurious lead and 12.8 dB of gain at f_s/2, while backward Euler and matched pole-zero mapping lose 12° and 4° of lead. The zero-order-hold equivalent overstates the gain by 4.65 dB because step invariance treats the controller's input as held between samples, which a sampled measurement is not; the method suits plant models rather than controllers.

From the Continuous Law to Code

Åström and Murray give an implementation along these lines, run once per sampling period T:

1. Proportional term: P[k] = K_p(b r[k] − y[k]), where the setpoint weight b, between 0 and 1, changes the response to setpoint steps without changing the response to disturbances.
2. Derivative term, filtered and acting on the measurement only: D[k] = [T_f/(T_f + T)]D[k − 1] − [K_d/(T_f + T)](y[k] − y[k − 1]).
3. Output: v[k] = P[k] + I[k] + D[k], then u[k] = sat(v[k]), clipped to the actuator's limits and sent at once.
4. Integral update, for use at the next sample: I[k + 1] = I[k] + K_iT e[k] + (T/T_t)(u[k] − v[k]), where the last term provides anti-windup, described in the next section.

Precomputing the coefficients leaves only a few multiplications and additions per sample.

Filtering the Derivative

An ideal derivative has gain that rises without limit, so measurement noise would dominate it. The term K_ds therefore becomes K_ds/(1 + sT_f), and Åström and Murray suggest T_f = T_d/N with N between 5 and 20, where T_d = K_d/K_p. The backward difference used above is the safe discretization: its coefficient T_f/(T_f + T) lies between 0 and 1 for every sampling period, so the derivative filter is always stable. A forward difference gives the pole 1 − T/T_f instead, which leaves the unit circle when T > 2T_f. Taking the derivative of the measurement rather than of the error also prevents a spike in the output each time the setpoint steps.

Position and Velocity Forms

The implementation above is the position form, which computes the whole output every sample. The velocity, or incremental, form computes only the change. With a backward-difference integral and an unfiltered derivative, it is

Δu[k] = K_p(e[k] − e[k − 1]) + K_iT e[k] + (K_d/T)(e[k] − 2e[k − 1] + e[k − 2])

and the controller adds Δu[k] to the previous output. If the stored previous output is the clipped value actually applied, the integral cannot wind up, and a switch from manual to automatic starts from the actuator's present value without a bump. The velocity form needs integral action; without it, every increment lost at a limit shifts the output's offset permanently.

How Windup Happens

Every actuator saturates somewhere, from an inverter limited by its DC link to a valve that is fully open. While the actuator sits at a limit, the loop is effectively open, yet the integral term keeps accumulating an error it cannot correct. When the error finally reverses, the oversized integral holds the actuator at its limit, and the output overshoots while the integral unwinds.

Conditional Integration

Clamping, the common digital form of conditional integration, freezes the integral whenever the output is saturated and the error has the sign that would push it further into saturation. Another variant integrates only while the error is small; Åström and Murray use it in an exercise to show the difficulty of introducing such ad hoc nonlinearities without careful analysis.

Back-Calculation

Back-calculation, also called tracking, feeds the difference between the applied and unsaturated outputs back into the integrator, as the last term of the integral update above does. Without saturation, u = v and the term vanishes. In saturation, it pulls the integral toward the value that places v at the limit, with the tracking time constant T_t, so the output leaves the limit as soon as the error changes sign. A short T_t resets the integral quickly, but too short a value lets measurement noise reset it as well. The saturation inside the controller must match the real limit: in a motor drive whose two current controllers share one voltage limit, each integrator must see the voltage actually applied, as the drive-oriented Control Algorithms article discusses.

Bumpless Transfer

A bump is a step in the actuator command caused by the controller rather than the plant. The remedies are these:

• Manual to automatic: set I = u_manual − P − D at the moment of transfer, or keep the controller running in manual with its back-calculation term driven by the manual output, so that v already equals the actuator's value.
• Parameter changes: store I in output units rather than as a sum of errors, so that a change in K_i affects only future increments. When K_p or b changes, add the old P minus the new P to I at the same sample.
• Switching between controllers, as in gain scheduling or the constant-voltage and constant-current modes of a programmable supply: initialize the incoming controller's integral so that its first output equals the outgoing controller's last.
• Velocity form: bumpless by construction.

The Closed-Loop Characteristic Equation

With the plant's zero-order-hold equivalent G(z), a computation delay of d samples, and the controller C(z), the closed-loop poles are the roots of

1 + C(z) z^−d G(z) = 0

and the loop is stable when every root lies strictly inside the unit circle. A delay of d samples puts d poles at the origin of the loop gain and raises the order of the characteristic polynomial by d. The stability triangle in Z-Transform tests a second-order polynomial by its coefficients, and the Jury test extends it to higher orders.

Sampling and Delay Can Destabilize a Simple Loop

Proportional control of an integrating plant, K/s, is stable at any gain in continuous time. Sampled through a hold, the plant becomes G(z) = KT/(z − 1). Write ω_c = K_pK for the crossover frequency of the continuous loop:

• Without computation delay, the closed-loop pole lies at z = 1 − ω_cT. The loop is stable only for ω_cT < 2, that is, for f_c < f_s/π. At ω_cT = 1 the pole sits at the origin and the output settles in one sample; beyond that the pole turns negative and the response alternates.
• With one sample of computation delay, the characteristic equation becomes z² − z + ω_cT = 0, which the stability triangle passes only for ω_cT < 1. One sample of delay halves the usable gain.

The approximation treats the hold as a delay of T/2 and the computation as a further T. It stays within half a degree down to f_s = 12.6f_c, but it reports 4.1° and 32.7° of margin for the two marginally stable loops. Below about ten samples per crossover period, check a design with the exact discrete model.

Reading Damping and Speed from Pole Locations

Through z = e^sT, a continuous pole pair with damping ratio ζ and natural frequency ω_n maps to the radius and angle

r = e^−ζω_nT and θ = ω_nT√(1 − ζ²)

and, with θ in radians, the inverse relations are ζ = −ln r/√(ln² r + θ²) and ω_n = √(ln² r + θ²)/T. Curves of constant damping are logarithmic spirals that start at z = 1 and wind toward the origin, and the 2 percent settling time is roughly 4/(−ln r) samples. In the current-loop example below, the poles 0.500 ± j0.301 at f_s = 10 kHz have r = 0.584 and θ = 31.0°, so ζ = 0.705, f_n = 1.22 kHz, and the settling estimate is 7.4 samples. A root locus drawn in the z-plane follows the same construction rules as one in the s-plane; only the stability boundary and these contours differ.

Resolution in the Units That Matter

An ADC with N bits and full scale V_FS resolves V_FS/2^N at its input, which, divided by the sensor gain, gives its resolution in plant-output units. A digital PWM (DPWM) resolves one clock count. In a buck converter in continuous conduction, whose output is V_out = DV_in, one count of an N_c-count period changes the output by V_in/N_c. Whether the loop can settle depends on how the two compare in plant-output units.

Conditions for Quantization Limit Cycles

A loop with integral action drives its digital error to zero, but the ADC reads zero error across a band one step wide around the reference, the zero-error bin, and the DPWM produces only discrete levels. If no level puts the output inside the bin, the loop has no equilibrium: the integral hunts between neighboring levels, and the output settles into a steady oscillation, a limit cycle. Angel Peterchev and Seth Sanders proposed conditions for avoiding it at the 2001 IEEE Power Electronics Specialists Conference and in IEEE Transactions on Power Electronics in January 2003. Hao Peng, Dragan Maksimović, Aleksandar Prodić, and Eduard Alarcón extended the analysis with describing functions at the 2004 conference. For a loop whose only quantizers are the ADC and the DPWM, the conditions are these:

1. The DPWM step, referred to the output, is smaller than the ADC step, so that a DPWM level falls inside the zero-error bin. Peterchev and Sanders judged one extra bit of DPWM resolution, two levels per ADC step, sufficient in most applications.
2. The control law includes integral action, with a gain above zero and no greater than one, counted in DPWM steps per ADC step per sample, so that the integrator can adjust the duty cycle by single counts (Peterchev and Sanders). Peng and his colleagues add that a large but finite DC gain can leave the loop with no DC solution, so that a limit cycle results.
3. The loop must not oscillate when the effective gain of the ADC, which its describing function puts as high as about 1.3, multiplies the loop gain (Peterchev and Sanders). Peng and his colleagues extended this test to both quantizers: when an oscillation would span three or more DPWM levels, neither effective gain exceeds 4/π, so the linear loop needs a gain margin above (4/π)², about 1.62 or 4.2 dB.
4. A toggle between two adjacent DPWM levels, where the modulator's effective gain can be very large, must produce a fundamental smaller than half an ADC step at the ADC input, at the frequency where the loop phase reaches −180° (Peng and his colleagues). This condition matters most with a slow integral compensator.

Peng and his colleagues also warn that non-sinusoidal limit cycles can still occur when the resolution or gain-margin condition holds only narrowly. In practice the conditions call for high-resolution DPWM, which designers obtain from fast counters, from delay lines that place edges between clock ticks, or from dither. Dither alternates between adjacent counts over a pattern of several periods to create intermediate average levels, and it trades resolution for low-frequency ripple, because a pattern of 2^m periods repeats at f_s/2^m.

Fixed-Point Scaling

Fixed-point controllers represent each signal as an integer with an implied binary point, in the Q formats described in Fixed-Point Implementation and Quantization Effects. Three rules matter most in a control loop:

• Scale every signal so that its largest expected value fits with headroom, and saturate rather than wrap on overflow. A wrapped value reverses sign inside the loop and can drive a large oscillation.
• Give the integrator more fractional bits than the output. Suppose the integral gain is 0.01 DPWM count per ADC step per sample. An integrator stored in whole counts, with each increment rounded to the nearest count, discards every error smaller than 50 ADC steps, so the loop can rest that far from its reference. With 16 extra fractional bits, a one-step error adds 655/65,536 count per sample, and the integral advances one count in about 100 samples, as designed.
• Round rather than truncate. An arithmetic right shift rounds toward minus infinity, turning a small positive increment into 0 and a small negative one into −1, so the integral drifts in one direction.

Structure of a Control Interrupt

Most embedded controllers run the loop in an interrupt synchronized to the PWM:

1. The PWM timer triggers the ADC at a chosen point in the carrier, so sampling is locked to switching without software jitter.
2. The ADC's end-of-conversion interrupt, at top priority, starts the control routine.
3. The routine scales the samples, checks protection limits, evaluates the control law, and saturates the result.
4. It writes the new compare values into the PWM's shadow registers, which the timer loads at the next period boundary, so the update instant stays fixed however long the code runs.
5. Outer loops, communication, and logging run at lower priority or at submultiples of the sample rate.

The worst-case execution time, not the average, must fit before the load instant. Real-Time Features describes the interrupt handling and timer peripherals that make this schedule possible.

Microcontrollers and Digital Signal Processors

Microcontrollers and digital signal processors aimed at motor control and power conversion combine a processor core with PWM timers, ADC triggers, and fault inputs. A hardware floating-point unit removes most scaling work but none of the need for anti-windup, saturation, or care with poles near z = 1. Fixed-point arithmetic remains common in the lowest-cost devices and the fastest loops.

FPGAs and Dedicated Controllers

An FPGA evaluates the control law in parallel logic, so its computation delay can be a small fraction of the sampling period, and it can sample once per switching period in converters that switch at several megahertz. The costs are hardware arithmetic design, pipelining, and verification effort; FPGA Implementation Techniques covers pipelining and DSP-block inference. Many dedicated digital power controllers take a middle path, implementing the ADC, the compensator, and a high-resolution DPWM in fixed hardware and leaving configuration, telemetry, and communication to a small processor.

Verification

Processor-in-the-loop testing runs the real code against a simulated plant, and hardware-in-the-loop testing runs the real controller against a real-time plant model. On finished hardware, firmware can measure the loop gain by injecting a small sine wave at a summing point in the control law and comparing the signals on either side of it, the digital form of the injection method described in Stability Analysis and Compensation.

A Digital Power-Supply Voltage Loop

A buck converter steps 12 V down to 3.3 V, switching at 250 kHz with trailing-edge modulation. The controller samples the output at the start of each period and loads each new duty cycle at the start of the next. A 12-bit ADC with a 3.3 V full scale reads the output through a divider of one half. The design targets a crossover frequency of 12.5 kHz, f_s/20.

1. Delay. The duty cycle is D = 3.3/12 = 0.275, and T = 4 µs. One period between sampling and loading, plus the trailing-edge delay DT = 1.1 µs, gives 5.1 µs. At 12.5 kHz that costs 360° × 12,500 Hz × 5.1 µs, about 23°, so an analog compensator designed for 60° of phase margin would keep only 37°.
2. ADC resolution. One step is 3.3 V/4,096 = 0.806 mV at the ADC input, or 1.61 mV at the output.
3. DPWM resolution. A 100 MHz counter gives 400 counts per period, so one count moves the output by 12 V/400 = 30 mV, 18.6 times the ADC step. This loop would limit-cycle.
4. Resolution requirement. For one DPWM step to fall below one ADC step, the modulator needs more than 7,447 levels, which means edge placement finer than 537 ps. With the margin of two, it needs edges finer than about 270 ps; a delay-line or high-resolution PWM with 250 ps steps gives 16,000 levels and 0.75 mV per step. Five bits of dither on the 400-count counter would give 12,800 levels and 0.94 mV, which meets the basic condition but not the margin, and its 32-period pattern would repeat at 7.8 kHz, below the crossover frequency.
5. Discretization and verification. Tustin's method, prewarped at 12.5 kHz, converts the analog compensator, and an exact discrete model with the 5.1 µs delay confirms the margins. The gain margin must also clear the 4.2 dB quantization condition, and the integral gain must stay within one DPWM step per ADC step per sample.

A Motor Current Loop

One axis of a permanent-magnet motor's current loop is modeled as R = 0.5 Ω in series with L = 1 mH, an electrical time constant of 2 ms, with the back-EMF treated as a slowly varying disturbance. The inverter can apply ±24 V. Symmetric PWM runs at 10 kHz, the current is sampled at a carrier peak, and each new voltage command loads one period later, so the total delay is 1.5T = 150 µs.

1. Emulation design. A PI controller whose zero cancels the electrical pole, K_i/K_p = R/L, reduces the loop gain to (ω_c/s)e^−1.5sT, whose phase margin is 90° minus 1.5ω_cT expressed in degrees. For 60°, ω_c = π/(9T) = 3,491 rad/s, so f_c = 556 Hz, or f_s/18. Then K_p = ω_cL = 3.49 V/A and K_i = ω_cR = 1,745 V/(A·s), so K_iT = 0.1745 V/A.
2. Predicted gain margin. The phase reaches −180° at 1,667 Hz, where the loop gain is 1/3, a gain margin of 9.5 dB.
3. Exact check. The zero-order-hold equivalent of the plant is b/(z − a), with a = e^−RT/L = 0.95123 and b = (1 − a)/R = 0.09754 A/V. With the delay z⁻¹ and a forward-Euler PI controller, the loop crosses over at 544 Hz with 60.4° of phase margin and 9.4 dB of gain margin, and the closed-loop bandwidth is 1.28 kHz.
4. Direct digital refinement. Placing the PI zero exactly on the discrete plant pole, K_iT/K_p = 1 − a, gives K_iT = 0.1702 V/A and reduces the loop gain to K_pb/[z(z − 1)]. The closed-loop poles solve z² − z + K_pb = 0 with K_pb = 0.3405, which places them at 0.500 ± j0.301. The loop stays stable up to K_pb = 1, or K_p = 10.25 V/A, a gain margin of 9.4 dB, and a small step overshoots by 4.6 percent and settles within 2 percent in 0.9 ms.
5. A large step. A step from 0 to 20 A needs 10 V in steady state, but the proportional term alone demands 69.8 V at the first sample. A sample-by-sample simulation with the emulation gains, zero back-EMF, and the ±24 V limit gives three outcomes. With no anti-windup, the current overshoots to 23.3 A, 16.5 percent, and takes 5.7 ms to settle within 2 percent. With clamping, the integral is still zero when the output leaves the limit, so the current slows near 18 A and creeps the rest of the way without overshoot, settling in 4.5 ms. Back-calculation with T_t equal to the 2 ms integral time gives 1.3 percent overshoot and settles in 1.2 ms.