Electronics Guide

Differential Nonlinearity (DNL)

Differential nonlinearity measures the deviation of each code transition width from the ideal value of one least significant bit (LSB). In an ideal converter, each digital code corresponds to exactly the same analog range, and incrementing the code by one always represents the same analog change. Real converters exhibit variations in step sizes.

DNL is expressed as:

DNL(k) = [V(k+1) - V(k)] / VLSB - 1

where V(k) is the analog value at code k and VLSB is the ideal step size. A DNL of zero indicates perfect step size; positive DNL means the step is wider than ideal, and negative DNL means it is narrower.

Key characteristics of DNL:

• Missing codes: DNL worse than -1 LSB indicates a missing code, where the converter skips a digital output value entirely
• Monotonicity guarantee: DNL better than -1 LSB ensures the converter is monotonic, meaning the output always increases (or stays the same) as input increases
• Histogram testing: DNL can be efficiently measured using histogram methods with ramping or dithered inputs
• Major code transitions: The largest DNL errors typically occur at major code transitions (powers of two) where the most significant internal elements switch

For a 16-bit converter with 2 V full-scale range, one LSB equals approximately 30.5 microvolts. A DNL specification of plus or minus 0.5 LSB means each step width falls between 15.3 and 45.8 microvolts.

Integral Nonlinearity (INL)

Integral nonlinearity quantifies the cumulative deviation of the actual transfer function from an ideal straight line. While DNL describes local step-to-step variations, INL captures the overall shape of the transfer function.

INL at code k can be calculated as the sum of DNL values up to that code:

INL(k) = sum of DNL(i) for i from 0 to k-1

Alternatively, INL is often specified relative to a best-fit straight line or an endpoint line that connects the first and last codes. The best-fit approach typically yields smaller INL values because it optimizes the reference line position and slope.

INL characteristics:

• Bow shape: INL often exhibits a characteristic bow shape, accumulating through the code range and returning toward zero at full scale
• Architecture dependence: Different converter architectures produce characteristic INL patterns; pipeline ADCs may show discontinuities at stage boundaries
• Temperature sensitivity: INL often varies with temperature as internal component matching changes
• Relationship to accuracy: INL directly limits the absolute accuracy of the conversion; a 10-LSB INL error means the digital output could be wrong by up to 10 counts

Offset Error

Offset error represents a constant shift in the transfer function, displacing all codes by the same amount. An ideal converter produces its first code transition at exactly 0.5 LSB above analog zero; offset error shifts this transition point.

Sources of offset error include:

• Comparator offset: Input offset voltage of the comparison circuits
• Reference offset: Errors in the reference voltage generation or distribution
• Input stage offset: DC errors in buffer amplifiers or input networks
• Leakage currents: Offset-inducing currents in high-impedance nodes

Offset error is typically specified in LSBs or as a percentage of full scale. Unlike INL and DNL, offset error can often be calibrated out by subtracting a stored correction value from each conversion result.

Gain Error

Gain error describes the deviation of the transfer function slope from the ideal value. An ideal converter spans exactly the specified full-scale range; gain error causes the span to be slightly larger or smaller.

Gain error is typically measured after offset correction and is expressed as:

Gain Error = (Actual Span / Ideal Span - 1) x 100%

or equivalently in LSBs at full scale.

Sources of gain error:

• Reference voltage error: The primary source; reference accuracy directly determines gain accuracy
• Resistor ratio errors: In resistive divider-based converters, matching errors affect gain
• Temperature drift: Reference and resistor temperature coefficients cause gain drift
• Loading effects: External loading on reference or output stages can alter gain

Like offset, gain error can often be calibrated by scaling the digital output. Many precision applications perform both offset and gain calibration using known reference inputs.

Monotonicity

A monotonic converter guarantees that the output always increases (or at least stays the same) as the input increases. For ADCs, this means larger analog inputs always produce equal or larger digital codes. For DACs, higher digital codes always produce equal or higher analog outputs.

Monotonicity is guaranteed when DNL is better than -1 LSB for all codes. Non-monotonic behavior causes serious problems in feedback control systems, where a controller might oscillate between codes that don't maintain proper ordering.

Some converter architectures inherently guarantee monotonicity:

• Thermometer-coded DACs: Always monotonic because elements are only added, never subtracted
• Integrating ADCs: Inherently monotonic due to their integration-based conversion
• Delta-sigma converters: Generally monotonic due to their oversampled, noise-shaped operation

Signal-to-Noise Ratio (SNR)

Signal-to-noise ratio measures the ratio of signal power to noise power within the Nyquist bandwidth, excluding harmonic distortion components. It captures the fundamental noise limitation of the converter.

SNR = 10 x log10(Psignal / Pnoise) dB

For an ideal converter, quantization noise sets the SNR limit. The theoretical maximum SNR for an N-bit converter is:

SNR(ideal) = 6.02N + 1.76 dB

This formula shows that each additional bit of resolution adds approximately 6 dB to the SNR. A 16-bit converter theoretically achieves 98.1 dB SNR; a 24-bit converter reaches 146.2 dB.

Real converters achieve lower SNR due to:

• Thermal noise: From resistors, transistors, and other components in the signal path
• Quantization noise: The fundamental noise from amplitude discretization
• Reference noise: Noise on the voltage reference appears directly in the output
• Clock jitter: Timing uncertainty converts to amplitude uncertainty (discussed separately)
• Power supply noise: Coupling from supply rails into the analog signal path

Signal-to-Noise and Distortion Ratio (SINAD)

SINAD combines noise and distortion into a single figure of merit, measuring the ratio of signal power to the sum of all noise and distortion power:

SINAD = 10 x log10(Psignal / (Pnoise + Pdistortion)) dB

SINAD provides the most complete single-number characterization of converter dynamic performance because it captures all error sources that degrade signal quality. It directly relates to the effective number of bits (ENOB) specification.

SINAD is always less than or equal to SNR, with equality only when distortion is negligible. The relationship between SINAD, SNR, and THD follows:

1/SINAD = 1/SNR + 1/(THD ratio) (in linear terms, not dB)

Total Harmonic Distortion (THD)

Total harmonic distortion measures the ratio of harmonic distortion power to fundamental signal power, typically including harmonics up to the fifth or higher:

THD = sqrt(V2^2 + V3^2 + V4^2 + ...) / V1

where V1 is the fundamental amplitude and V2, V3, etc., are harmonic amplitudes.

THD is usually expressed in dB (negative values) or as a percentage:

THD(dB) = 20 x log10(THD ratio)

Sources of harmonic distortion in converters:

• INL errors: Nonlinearity in the transfer function generates harmonics of the input signal
• Comparator nonlinearity: Nonlinear behavior of internal comparators
• Capacitor nonlinearity: Voltage-dependent capacitance in switched-capacitor circuits
• Amplifier distortion: Nonlinearity in internal or external buffer amplifiers
• Reference nonlinearity: Load-dependent reference voltage variations

THD typically worsens at higher frequencies and larger signal amplitudes. Datasheets often specify THD versus frequency curves to capture this behavior.

Spurious-Free Dynamic Range (SFDR)

Spurious-free dynamic range measures the ratio of signal power to the largest spurious spectral component, whether that component is a harmonic, intermodulation product, or other spur:

SFDR = 10 x log10(Psignal / Plargest_spur) dB

SFDR is particularly important in communication and spectroscopy applications where any spurious signal might be mistaken for a real signal. Unlike THD, which averages multiple harmonics, SFDR focuses on the single worst offender.

SFDR can be limited by:

• Harmonic distortion: Often the second or third harmonic is the largest spur
• Intermodulation products: With multi-tone inputs, mixing products may exceed harmonics
• Clock feedthrough: Coupling of sampling clock harmonics into the output spectrum
• Digital feedthrough: Coupling from digital output switching
• Power supply spurs: Mixing between supply noise and signal

High-performance ADCs for software-defined radio and instrumentation require SFDR exceeding 80 or 90 dB to distinguish weak signals from conversion artifacts.

Noise Power Ratio (NPR)

Noise power ratio characterizes converter performance with wideband signals by using a notched noise stimulus. The converter is driven with band-limited noise containing a narrow notch, and NPR measures how much the converter fills in the notch with distortion products:

NPR = 10 x log10(Pnotch_floor / Pnoise_outside_notch) dB

NPR better represents performance with complex wideband signals than single-tone testing because it captures intermodulation between many frequency components simultaneously. It is commonly used to characterize converters for OFDM and other multi-carrier communication systems.

ENOB Calculation

ENOB is calculated from SINAD using the inverse of the ideal converter SNR formula:

ENOB = (SINAD - 1.76) / 6.02 bits

For example, a converter with 72 dB SINAD has ENOB = (72 - 1.76) / 6.02 = 11.67 bits. Despite potentially being marketed as a 14-bit or 16-bit converter, its actual dynamic performance matches that of an ideal 11.67-bit device.

ENOB provides an intuitive interpretation of dynamic performance. A 16-bit converter with 12-bit ENOB has four bits of resolution degraded by noise and distortion, delivering only 4096 distinguishable levels rather than the theoretical 65,536.

Factors Affecting ENOB

ENOB varies with operating conditions:

• Input frequency: ENOB typically decreases at higher input frequencies as distortion increases and jitter effects grow
• Sampling rate: Some converters show improved ENOB at lower sampling rates due to reduced settling-related errors
• Input amplitude: ENOB may peak below full scale where distortion is minimized
• Temperature: Thermal noise increases with temperature, reducing ENOB
• Clock quality: Jitter degrades ENOB, especially at high input frequencies

Datasheets typically specify ENOB at specific test conditions (input frequency, sampling rate, amplitude). Performance at other conditions may differ significantly, so testing under actual application conditions is important for critical applications.

ENOB vs. Resolution

The marketing resolution of a converter (e.g., "16-bit ADC") indicates the digital word width but says nothing about actual conversion accuracy. ENOB provides the reality check:

• High-speed converters: A 14-bit pipeline ADC at 100 MSPS might achieve 11.5 ENOB at Nyquist input frequency
• Precision converters: A 24-bit delta-sigma ADC at 10 SPS might achieve 20 ENOB or better
• Audio converters: Quality 24-bit audio ADCs typically achieve 19 to 21 ENOB in the audio band
• High-frequency limits: ENOB often drops by several bits as input frequency approaches the Nyquist limit

When comparing converters, ENOB at the actual application conditions provides a more meaningful comparison than resolution alone.

Jitter-Induced Noise

For a sinusoidal input signal, the voltage error caused by timing uncertainty is:

Verror = 2 x pi x fin x Vp x tj

where fin is the input frequency, Vp is the signal amplitude, and tj is the RMS jitter. This error increases linearly with input frequency, making jitter increasingly important at higher frequencies.

The SNR degradation due to jitter alone is:

SNR(jitter) = -20 x log10(2 x pi x fin x tj)

For example, with 1 ps RMS jitter and a 100 MHz input signal:

SNR(jitter) = -20 x log10(2 x pi x 100e6 x 1e-12) = 64 dB

This represents the jitter-limited SNR ceiling regardless of converter resolution.

Jitter Sources

Total jitter in a sampling system comes from multiple sources:

• Converter aperture jitter: Internal timing uncertainty in the sample-and-hold circuit, typically specified in datasheets
• Clock source phase noise: Random phase fluctuations in the sampling clock oscillator
• Clock distribution jitter: Added jitter from clock buffers, transmission lines, and noise coupling in the clock path
• Power supply noise: Supply variations that modulate internal delay paths

For high-frequency applications, external clock quality often dominates over internal aperture jitter. A low-jitter clock source with clean distribution becomes essential.

Clock Requirements

To prevent jitter from limiting ENOB, the total jitter must satisfy:

tj less than 1 / (2 x pi x fin x 10^(6.02N/20))

where N is the desired ENOB. For a 14-bit converter (84 dB SNR) sampling a 100 MHz signal:

tj less than 100 femtoseconds

This extremely tight requirement explains why high-speed, high-resolution conversion demands exceptional clock quality. Strategies to meet these requirements include:

• Low-noise crystal oscillators: Fundamental mode crystals in optimized oscillator circuits
• Dedicated clock generators: Specialized ICs designed for low jitter
• Short clock paths: Minimize jitter-adding elements between clock source and converter
• Filtered clock: Bandpass filtering near the clock frequency removes broadband noise
• Isolated clock power: Separate, low-noise power supply for clock circuitry

Two-Tone Testing

The standard two-tone test applies two equal-amplitude sinusoids at frequencies f1 and f2. Nonlinearity generates intermodulation products at frequencies:

• Second-order products: f1 + f2, f1 - f2, 2f1, 2f2
• Third-order products: 2f1 - f2, 2f2 - f1, 2f1 + f2, 2f2 + f1
• Higher-order products: nf1 +/- mf2 for various n, m

Third-order intermodulation products at 2f1 - f2 and 2f2 - f1 are particularly problematic because they fall close to the original signals in frequency, making them difficult to filter.

Third-Order Intercept Point

The third-order intercept point (IP3 or TOI) characterizes third-order intermodulation strength. It is the extrapolated input power at which the third-order products would equal the fundamental signal power (this power level is never actually reached because the converter saturates first).

Higher IP3 indicates better linearity and lower intermodulation. The relationship between input power, output power, and IP3 follows:

IMD3 = Pout - 2(IP3 - Pin)

where all values are in dBm or dB. This shows that IMD3 products grow at three times the rate of the fundamental signal with increasing input level.

IMD in Communication Systems

Intermodulation distortion is critical in communication receivers where signals at different frequencies must be processed simultaneously without creating interfering products. Key considerations include:

• Adjacent channel interference: IMD products falling in adjacent communication channels
• Desense: Strong signals generating IMD products that mask weak desired signals
• Spurious response: IMD products appearing as false signals
• Dynamic range: The range between the weakest detectable signal and the strongest signal that can be processed without excessive IMD

Software-defined radio applications require converters with high IP3 to handle the diverse signal environment without generating spurious responses.

Power Supply Rejection Ratio

Power supply rejection ratio (PSRR) quantifies the converter's immunity to supply variations:

PSRR = 20 x log10(delta_VDD / delta_Vout) dB

Higher PSRR values indicate better rejection of supply variations. PSRR typically varies with frequency, often degrading at higher frequencies where internal bypass capacitors become less effective.

Different supply pins may have different PSRR values:

• Analog supply: Directly affects the analog signal path; high PSRR critical
• Digital supply: Primarily affects digital logic; noise couples through substrate and ground
• Reference supply: Often the most sensitive; reference noise appears directly in output
• I/O supply: Affects digital output drivers; can couple back to analog circuitry

Supply Noise Effects

Power supply noise affects converter performance through several mechanisms:

• Reference modulation: Supply noise on reference circuits directly modulates conversion gain
• Comparator threshold modulation: Supply variations shift comparator switching points
• Timing modulation: Supply-dependent delays cause jitter
• Substrate coupling: Noise injected through the substrate affects sensitive analog nodes
• Ground bounce: Current transients cause local ground potential variations

The frequency relationship between supply noise and signal frequency determines whether the corruption appears as gain modulation, added noise, or spurious tones. Low-frequency supply variations modulate the gain, while supply noise near the signal frequency creates sidebands.

Decoupling Strategies

Effective power supply decoupling is essential for achieving datasheet performance:

• Multiple capacitor values: Use parallel capacitors covering different frequency ranges (10 microfarads, 100 nanofarads, 10 nanofarads)
• Close placement: Place decoupling capacitors as close as possible to power pins
• Low-ESR capacitors: Ceramic capacitors provide low impedance at high frequencies
• Ferrite beads: Isolate noisy digital supplies from sensitive analog supplies
• Separate regulators: Use dedicated low-noise regulators for analog and reference supplies
• Ground plane design: Solid ground planes with strategic split to separate analog and digital currents

Offset and Gain Drift

Offset and gain drift are typically specified in ppm/C or LSB/C:

• Offset drift: Caused by temperature coefficients of amplifier offset voltages, mismatched resistor temperature coefficients, and thermoelectric effects
• Gain drift: Primarily determined by reference voltage temperature coefficient and resistor ratio temperature tracking

For a 16-bit converter with a 2 V span (30.5 microvolts/LSB) and 1 ppm/C gain drift, the gain changes by 2 microvolts or about 0.066 LSB per degree Celsius. Over a 50-degree temperature range, this accumulates to 3.3 LSB of gain error.

Precision applications require:

• Low-drift voltage references: References with temperature coefficients below 5 ppm/C
• Matched resistor networks: Thin-film networks with tracking temperature coefficients
• Temperature-stable amplifiers: Chopper or auto-zero amplifiers to eliminate offset drift
• Temperature compensation: Active compensation using temperature sensors and calibration tables

Reference Voltage Drift

The voltage reference is often the dominant source of temperature-dependent gain error. Different reference types offer different temperature performance:

• Bandgap references: Typical TC of 20 to 100 ppm/C without trimming; precision types achieve below 10 ppm/C
• Buried zener references: Excellent stability below 2 ppm/C, but require more complex circuitry
• XFET references: Advanced architectures achieving sub-ppm/C performance

External reference temperature coefficient directly multiplies the converter's effective gain drift, so reference selection is critical for temperature-sensitive applications.

Dynamic Parameter Drift

Dynamic specifications also vary with temperature:

• Noise: Thermal noise increases as the square root of absolute temperature; a 20% temperature increase raises noise by about 10%
• Bandwidth: Amplifier bandwidth and slew rate typically decrease at temperature extremes
• INL and DNL: Internal component matching degrades with temperature, often worsening linearity
• THD: Distortion may increase at temperature extremes due to amplifier and comparator degradation

Datasheet specifications are usually given at 25 C; performance at temperature extremes may be significantly worse. Critical applications require characterization over the full operating temperature range.

Histogram Testing

Histogram testing efficiently measures DNL and INL by applying a slowly varying input signal and counting how many times each output code occurs. An ideal converter produces a uniform histogram with equal counts per code; deviations reveal DNL errors.

For a linear ramp input, the code occurrence probability is proportional to the code width:

DNL(k) = [Count(k) / Average_Count] - 1

INL is then calculated by integrating the DNL values.

Histogram test advantages:

• Speed: Tests all codes simultaneously rather than sequentially
• Statistical accuracy: Averaging over many samples reduces measurement uncertainty
• Ramp or noise input: Works with linear ramps or dithered signals
• Self-calibrating: Uses the converter's own output to determine code statistics

The number of samples required for a given accuracy depends on the desired confidence level. Typically, at least 16 or 32 samples per code provide adequate statistics for most production requirements.

FFT-Based Testing

Fast Fourier transform analysis efficiently extracts multiple dynamic specifications from a single test waveform. A sinusoidal input is digitized, and FFT analysis reveals the signal, noise floor, harmonics, and spurious components.

From a single coherent FFT acquisition, the following specifications can be calculated:

• SNR: Signal power divided by total noise power (excluding harmonics)
• THD: Harmonic power divided by signal power
• SINAD: Signal power divided by noise plus distortion power
• SFDR: Signal power divided by largest spur power
• ENOB: Calculated from SINAD

Coherent sampling (integer number of input cycles in the acquisition window) eliminates spectral leakage that would corrupt measurements. This requires precise frequency relationships between the sampling clock and signal generator.

Reduced Test Coverage

Full specification testing at every code and condition would require impractical test times. Production testing typically uses reduced coverage strategies:

• Correlation: Test a subset of parameters that correlate with others; passing the subset implies passing the full set
• Major code testing: Test only at major code transitions (powers of two) where errors typically peak
• Spot frequency testing: Test dynamic specifications at a few representative frequencies rather than full sweeps
• Room temperature testing: Test at 25 C only, using characterization data to guarantee temperature extremes
• Built-in self-test: Use on-chip circuitry to perform basic tests without external equipment

Automatic Test Equipment

Production testing requires specialized automatic test equipment (ATE) capable of generating precision signals and accurately measuring converter outputs:

• Source requirements: Low-distortion, low-noise signal generators with better linearity than the device under test
• Timing accuracy: Low-jitter clocks and precise phase control for coherent sampling
• Measurement accuracy: ADC testers need DACs better than the device under test, and vice versa
• Throughput: Parallel testing of multiple devices to reduce cost per device
• Temperature control: Capability to test at temperature extremes for characterization

ATE systems for high-resolution converter testing represent significant investments, and test methodology directly affects manufacturing cost. Optimizing the trade-off between test coverage and test time is an ongoing engineering challenge.

Specification Selection

Different applications prioritize different specifications:

• Precision measurement: INL, DNL, offset and gain accuracy, temperature drift
• Audio: THD, SNR, SINAD within the audio band (20 Hz to 20 kHz)
• Communication: SFDR, IMD, IP3, noise power ratio at the operating frequency
• High-speed data acquisition: ENOB vs. frequency, aperture jitter, input bandwidth
• Control systems: Monotonicity, settling time, latency

Testing vs. Datasheet Conditions

Datasheet specifications are measured under optimized conditions that may differ from application conditions:

• Input signal: Pure sinusoids vs. complex application signals
• Power supplies: Clean laboratory supplies vs. noisy system supplies
• Clock source: Low-jitter laboratory generators vs. system clocks
• Layout: Evaluation board vs. application PCB
• Temperature: 25 C vs. actual operating temperature

Application testing under actual conditions often reveals performance gaps that require design improvements or specification derating.

Margin and Guard Bands

Robust system design includes margin for specification variation:

• Production variation: Datasheet specifications represent limits; typical values are usually better
• Temperature variation: Allow for drift over the operating temperature range
• Aging: Some specifications drift over time, particularly precision references
• Application conditions: Real systems rarely achieve evaluation board performance

A common approach allocates performance budget with margin, targeting application requirements that are comfortably better than minimum datasheet specifications.