Built-In Self-Test for Analog

Introduction

Built-In Self-Test (BIST) for analog circuits represents one of the most challenging frontiers in test engineering. Unlike digital BIST, where well-established techniques like scan chains and pattern generators achieve high fault coverage with minimal area overhead, analog BIST must contend with continuous signal levels, parametric variations, and performance metrics that span frequency, noise, linearity, and dynamic range. Yet the economic pressures driving analog BIST development are compelling: external test equipment for analog circuits is expensive, test times are long, and the growing integration of analog functions into complex systems-on-chip makes external access increasingly difficult.

Analog BIST embeds test stimulus generation, response analysis, and pass/fail decision-making directly within the integrated circuit. When implemented successfully, it enables wafer-level testing without expensive probe cards, field testing for maintenance and diagnostics, and continuous monitoring during operation. This section explores the architectures and techniques that make analog BIST practical, from on-chip signal generators to sophisticated response analyzers that can evaluate analog performance with digital efficiency.

On-Chip Test Signal Generation

Generating high-quality test stimuli on-chip is fundamental to analog BIST. The challenge lies in creating signals with sufficient accuracy, spectral purity, and flexibility using circuitry that adds minimal area and does not compromise the primary analog functions.

Digital-to-Analog Converter Based Generators

Digital-to-analog converters (DACs) provide flexible on-chip signal generation:

Direct digital synthesis: Generate arbitrary waveforms by clocking digital samples through a DAC, enabling sinusoids, ramps, and complex modulated signals
Sigma-delta modulators: Single-bit output simplifies the analog reconstruction while providing high resolution after filtering
Current-steering DACs: Fast settling enables high-frequency signal generation with good spectral purity
R-2R ladder DACs: Area-efficient implementation suitable for moderate resolution test signals

The key challenge is achieving sufficient spectral purity for testing high-performance analog circuits. The test generator must be significantly better than the circuit under test to avoid masking actual defects with stimulus imperfections.

Oscillator-Based Stimulus Generation

On-chip oscillators provide simple yet effective test signal sources:

Ring oscillators: Generate square waves at frequencies determined by delay chain length; useful for frequency response testing
LC oscillators: Provide cleaner sinusoidal outputs but require inductors that consume significant area
Relaxation oscillators: Generate triangular and square waves using capacitor charging and threshold detection
Crystal oscillators: When crystals are already present for system timing, they provide extremely stable reference frequencies

Frequency dividers and phase-locked loops can derive multiple test frequencies from a single oscillator, enabling multi-tone testing for intermodulation distortion measurement.

Pseudo-Random Sequence Generators

Linear feedback shift registers (LFSRs) generate pseudo-random binary sequences useful for analog testing:

Noise-like spectra: Filtered LFSR outputs approximate white noise for noise figure testing
Spread spectrum signals: Enable correlation-based measurements that reject interference
Multi-tone approximation: Long sequences contain many frequency components for simultaneous multi-frequency testing
Deterministic repeatability: Unlike true random sources, LFSR sequences are perfectly repeatable for correlation analysis

The mathematical properties of maximal-length sequences enable elegant analysis techniques where the response to the sequence reveals system characteristics through correlation.

Charge Injection and Current Pulse Generation

Simple switching circuits can generate precise charge packets and current pulses:

Switched capacitor injection: Transfer known charge packets to test charge-sensitive circuits
Current mirror pulses: Generate calibrated current steps using switched current mirrors
Edge-based stimulus: Fast digital transitions provide step and impulse approximations for transient testing
Ratiometric stimulus: Generate test signals as precise ratios of reference values using matched components

Response Analysis Techniques

Evaluating analog circuit responses on-chip requires converting continuous measurements into digital pass/fail decisions. The challenge is achieving sufficient measurement accuracy without replicating the complexity of external test equipment.

Analog-to-Digital Converter Based Analysis

On-chip ADCs enable direct digitization of analog responses:

Successive approximation ADCs: Moderate speed and resolution suitable for many DC and low-frequency measurements
Sigma-delta ADCs: High resolution at lower speeds for precision parametric measurements
Flash ADCs: High speed for capturing transient responses and high-frequency signals
Time-interleaved ADCs: Achieve high sample rates by combining multiple lower-speed converters

Once digitized, standard digital signal processing can compute gain, offset, distortion, and other performance metrics. The ADC resolution must exceed the measurement accuracy requirements, typically by at least two bits.

Window Comparator Analysis

Simple comparators provide efficient go/no-go testing:

Upper and lower limit detection: Verify signals remain within specification windows
Peak detection: Capture maximum signal excursions using diode-capacitor peak detectors
Threshold crossing timing: Measure when signals cross reference levels for timing parameter extraction
Programmable thresholds: DAC-generated reference levels enable flexible limit setting

Window comparators consume minimal area and power while providing immediate pass/fail indication. For many production test applications, this binary output suffices.

Amplitude and RMS Detection

Measuring signal amplitude is fundamental to many analog tests:

Rectifier-based detectors: Full-wave rectification followed by filtering provides average amplitude
True RMS detectors: Square, average, and square root operations yield RMS regardless of waveform shape
Log-ratio amplifiers: Compute ratios directly in the logarithmic domain for gain measurements
Synchronous detection: Multiply by reference and filter to extract amplitude and phase at specific frequencies

Synchronous detection using on-chip multipliers achieves excellent noise rejection by measuring only the coherent component at the stimulus frequency.

Phase and Frequency Measurement

Timing relationships reveal important performance characteristics:

Phase detector circuits: XOR gates or multipliers produce outputs proportional to phase difference
Time-to-digital converters: Count clock cycles or delay line taps between events for precise timing measurement
Frequency counters: Count zero crossings over defined intervals to measure frequency
Period averaging: Measure time for multiple cycles to improve frequency resolution

Signature Analysis for Analog Circuits

Signature analysis compresses circuit responses into compact digital signatures that can be compared against expected values. This technique, highly successful in digital testing, has been adapted for analog circuits with appropriate modifications.

Analog Signature Principles

Converting analog responses to signatures involves several approaches:

Digitized waveform signatures: Sample the analog response, compute a signature (CRC or checksum) over the digital samples
Feature extraction signatures: Extract specific features (peaks, zero crossings, slopes) and encode them digitally
Histogram signatures: Build amplitude histograms and compute statistical signatures from the distribution
Spectral signatures: Compute frequency domain representations and signature the spectral content

The key insight is that while exact analog values vary due to process and environmental variations, properly chosen signatures remain stable for functional circuits while changing dramatically for faulty ones.

Multiple Input Signature Registers

Multiple Input Signature Registers (MISRs) efficiently compress multiple bit streams:

Parallel signature compression: Multiple ADC outputs feed into a MISR simultaneously
Polynomial division: The LFSR structure performs polynomial division, creating a remainder that serves as the signature
Aliasing probability: The probability that a faulty circuit produces the correct signature is 2^(-n) for an n-bit MISR
Multiple signatures: Capture intermediate signatures to improve fault isolation when failures occur

Tolerance-Based Signature Analysis

Accommodating analog tolerances requires modified signature approaches:

Range encoding: Encode ADC outputs as ranges rather than exact values before signature computation
Differential signatures: Compute signatures on differences between channels, canceling common-mode variations
Statistical signature windows: Define acceptable signature ranges based on process variation analysis
Adaptive golden signatures: Update reference signatures based on measured good device populations

The tolerance window must be wide enough to pass good devices with normal variation but narrow enough to catch faulty devices with abnormal responses.

Oscillation-Based Testing

Oscillation-based test (OBT) converts analog circuits into oscillators and measures the oscillation frequency as an indicator of circuit health. This elegant technique transforms difficult analog measurements into simple frequency measurements that digital circuits handle efficiently.

Oscillation Test Principles

The fundamental concept exploits the relationship between circuit parameters and oscillation frequency:

Unity gain frequency: An amplifier with feedback will oscillate at the frequency where loop gain equals unity and phase shift equals 180 degrees
RC time constant: Oscillation frequency in RC oscillators directly reflects the RC product
Transconductance measurement: Oscillator frequency depends on active device transconductance, enabling parameter extraction
Filter characteristics: Converting filters to oscillators reveals their frequency response characteristics

A key advantage is that frequency measurement is inherently digital and can achieve high precision through simple counting over extended time intervals.

Oscillation Test Implementation

Practical oscillation test requires additional circuitry:

Feedback switching: Multiplexers reconfigure the circuit under test into an oscillator topology during test mode
Start-up circuits: Ensure reliable oscillation initiation, avoiding metastable states
Amplitude limiting: Control oscillation amplitude to maintain linear operation and prevent damage
Frequency counters: On-chip counters measure the oscillation frequency against a reference clock

Oscillation Test Applications

Various analog circuits are amenable to oscillation-based testing:

Operational amplifiers: Connect as relaxation oscillator to test gain-bandwidth product
Filters: Add feedback to create oscillator at cutoff frequency
Data converters: Use DAC and ADC in feedback loop, oscillation frequency indicates conversion linearity
Analog multiplexers: Include in oscillator path to verify switch resistance and bandwidth

The technique is particularly valuable for testing analog IP blocks embedded in large digital SoCs where external analog access is limited.

Limitations and Considerations

Oscillation testing has important limitations:

Fault coverage: Not all analog faults affect oscillation frequency; some defects may escape detection
Correlation to specifications: The relationship between oscillation frequency and datasheet parameters may be indirect
Additional circuitry: Feedback switches and control logic add area and potentially affect normal operation
Start-up time: Oscillators require settling time, which adds to test duration

Current Monitoring Techniques

Supply current monitoring, highly successful in digital IDDQ testing, has been adapted for analog circuits. Analog current monitoring reveals not only catastrophic faults but also parametric degradation and performance deviations.

Static Current Testing

Quiescent current measurement detects many fault types:

IDDQ testing: Measure static supply current; elevated current indicates defects such as gate oxide shorts or bridging faults
Multiple supply monitoring: Analog circuits often have separate analog and digital supplies requiring independent monitoring
Bias current verification: Compare measured bias currents against expected values for each operating mode
Leakage characterization: Identify excessive leakage that may indicate reliability concerns

Unlike digital IDDQ where only catastrophic faults cause elevated current, analog IDDQ must accommodate the larger variation in normal analog bias currents.

Dynamic Current Analysis

Time-varying current reveals additional information:

Transient current signatures: Current waveforms during state transitions reflect circuit timing and drive capability
AC current consumption: Measure current at various operating frequencies to verify frequency-dependent behavior
Current spectrum analysis: Frequency content of supply current reveals oscillations, instabilities, or abnormal modulation
Activity-dependent current: Correlate current consumption with circuit activity to identify abnormal dependencies

On-Chip Current Sensors

Various circuit techniques enable on-chip current measurement:

Series sense resistors: Small resistors in the supply path create voltage drops proportional to current
Current mirrors: Copy a scaled version of the supply current to a measurement circuit
Hall effect sensors: Magnetic field sensing enables non-contact current measurement in high-current applications
Built-in current sensors (BICS): Dedicated transistor structures that sample supply current without series resistance

The challenge is measuring current without significantly impacting circuit performance through added resistance or parasitic capacitance.

Current-Based Fault Detection

Current monitoring enables detection of various fault types:

Catastrophic faults: Opens and shorts cause dramatic current changes easily detected by simple comparators
Parametric faults: Gradual changes in bias currents indicate parameter drift or process variations
Intermittent faults: Continuous monitoring catches intermittent failures that might pass single-point testing
Reliability degradation: Trending current over time reveals wear-out mechanisms before functional failure

Process Monitors and Sensors

Process monitoring structures, fabricated alongside functional circuits, provide early indication of process variations that may affect circuit performance. These monitors enable adaptive testing and process-aware design optimization.

Ring Oscillator Monitors

Ring oscillators are widely used process monitors:

Speed monitors: Oscillation frequency directly indicates transistor switching speed
Multiple corner monitors: Separate oscillators using NMOS and PMOS transistors reveal individual corner positions
Voltage and temperature sensing: Frequency variation with supply voltage and temperature provides additional characterization
Local variation monitors: Multiple oscillators across the die reveal local process gradients

Ring oscillator frequencies correlate strongly with digital logic speed and can predict analog parameters like transconductance.

Analog Process Monitors

Structures specifically designed for analog parameter monitoring:

Reference voltage monitors: On-chip bandgap references provide process-compensated voltage standards
Threshold voltage monitors: Dedicated transistor structures enable accurate VT extraction
Matching monitors: Paired devices reveal local mismatch for critical analog specifications
Capacitor ratio monitors: Verify capacitor matching critical for switched-capacitor circuits

Environmental Sensors

On-chip sensors measure environmental conditions affecting performance:

Temperature sensors: Diode or bandgap-based sensors measure junction temperature
Voltage monitors: Supply voltage measurement enables voltage-compensated testing
Stress sensors: Piezo-resistive structures detect mechanical stress from packaging
Humidity sensors: Capacitive structures detect moisture ingress in some applications

Environmental sensors enable real-time compensation of measurements for accurate pass/fail determination regardless of test conditions.

Using Monitor Data

Process monitor data enables sophisticated test strategies:

Adaptive test limits: Adjust specification limits based on measured process corner
Correlation-based testing: Skip detailed tests when monitors indicate the device is well-centered
Binning decisions: Sort devices into speed grades or performance categories based on monitor data
Yield prediction: Use monitor data to predict which detailed tests are likely to fail

Degradation Detection

Detecting circuit degradation before functional failure enables predictive maintenance and improves system reliability. On-chip degradation monitoring is particularly valuable in safety-critical and high-reliability applications.

Aging and Wear-Out Mechanisms

Several mechanisms cause gradual circuit degradation:

Hot carrier injection: High-energy carriers become trapped in gate oxides, shifting threshold voltages over time
Bias temperature instability: Temperature-accelerated charge trapping causes VT drift in PMOS devices
Electromigration: Current-induced metal migration eventually causes open circuits in interconnects
Time-dependent dielectric breakdown: Gate oxide degradation that eventually leads to failure

These mechanisms progress gradually, enabling detection before catastrophic failure if appropriate monitoring is in place.

On-Chip Aging Monitors

Dedicated structures track degradation over device lifetime:

Stressed transistor monitors: Transistors under continuous bias stress track hot carrier and BTI degradation
Ring oscillator aging: Frequency drift over time indicates accumulated device degradation
Stress-aged references: Compare stressed and unstressed reference circuits to measure drift
Interconnect resistance monitoring: Track metal resistance increases indicating electromigration

In-Field Degradation Assessment

Monitoring during operation enables real-time degradation tracking:

Background monitoring: Continuously measure degradation indicators without interrupting normal operation
Periodic self-test: Run BIST sequences at scheduled intervals to assess current performance
Wear-out prediction: Project remaining useful life based on observed degradation rate
Graceful degradation: Reduce performance demands or switch to redundant circuits as degradation advances

Alarm and Reporting Systems

Communicating degradation status to the system level:

Threshold-based alarms: Generate interrupts when degradation exceeds predetermined levels
Degradation registers: Store degradation metrics accessible via system interfaces
Trend reporting: Provide degradation history enabling trend analysis
Predictive alerts: Warn of impending failure based on degradation trajectory

Self-Calibration Methods

Self-calibration extends BIST concepts beyond testing to correction, enabling circuits to compensate for process variations and drift. This approach improves yield by allowing wider process tolerance while maintaining tight performance specifications.

Calibration Architectures

Various approaches implement self-calibration:

Foreground calibration: Dedicated calibration phase during which normal operation is suspended
Background calibration: Continuous calibration that operates alongside normal circuit function
One-time calibration: Performed once during production test, with results stored in non-volatile memory
Continuous adaptation: Real-time adjustment responding to environmental and aging changes

Offset and Gain Calibration

Fundamental calibration targets in analog circuits:

Auto-zero amplifiers: Periodically sample and cancel offset using switched-capacitor techniques
Chopper stabilization: Modulate signals to move offset to high frequency where it can be filtered
Digital offset correction: Measure offset with on-chip ADC and subtract digitally or adjust DAC bias
Gain calibration: Compare against reference and adjust programmable gain elements

Linearity Calibration

Correcting nonlinearity in data converters and amplifiers:

Trim DAC adjustment: Programmable current or capacitor elements compensate for mismatch
Digital correction: Measure nonlinearity and apply correction in the digital domain
Redundant architectures: Over-ranging enables digital correction of analog errors
Segmented calibration: Calibrate different portions of the transfer function independently

High-resolution ADCs and DACs routinely employ self-calibration to achieve performance beyond what raw component matching would allow.

Timing Calibration

Adjusting timing relationships for optimal performance:

Clock phase adjustment: Programmable delay elements align clock phases for optimal sampling
Aperture calibration: Minimize sampling jitter by optimizing sample clock timing
Duty cycle correction: Adjust clock duty cycle for symmetric performance
Skew calibration: Compensate for timing differences between parallel channels

Calibration Storage and Management

Maintaining calibration data across power cycles:

On-chip fuses: One-time programmable elements store permanent calibration values
Non-volatile memory: EEPROM or flash stores calibration data that can be updated
External storage: System memory holds calibration values loaded at power-up
Re-calibration triggers: Temperature or time triggers initiate recalibration sequences

BIST Controller Architecture

Coordinating analog BIST operations requires a controller that sequences stimulus generation, response capture, and result evaluation. The controller may be dedicated hardware, shared digital logic, or software running on an embedded processor.

Control Sequencing

The BIST controller manages test execution:

Test mode entry: Configure the circuit for test mode, isolating sensitive nodes and enabling test access
Stimulus sequencing: Control signal generators to produce required test patterns in proper order
Timing control: Manage settling times, acquisition windows, and synchronization
Result collection: Gather response data and compute pass/fail determinations

Hardware versus Software Control

Tradeoffs between control implementations:

Dedicated state machine: Fixed hardware provides deterministic timing but limited flexibility
Microcode control: Programmable sequencer enables test modification without hardware changes
Processor-based control: Embedded CPU runs test software, maximizing flexibility at cost of speed
Hybrid approaches: Hardware handles time-critical operations while software manages sequencing

Result Reporting

Communicating BIST results to external systems:

Pass/fail flags: Simple status bits indicate overall test result
Diagnostic registers: Detailed results accessible via JTAG or other test interfaces
Signature readout: Compressed signatures available for external comparison
Parametric data: Measured values available for characterization and debugging

Design for Analog BIST

Successful analog BIST requires consideration during circuit design, not as an afterthought. Design for testability principles help ensure that BIST can achieve adequate fault coverage without compromising primary circuit performance.

Testability Guidelines

Design practices that enhance analog BIST effectiveness:

Observable nodes: Provide access to internal nodes critical for fault detection
Controllable inputs: Enable stimulus injection at multiple points within the circuit
Isolation capability: Include switches to isolate subsections for independent testing
Reference accessibility: Make internal reference voltages and currents measurable

Partitioning for Test

Dividing complex analog systems into testable blocks:

Functional partitioning: Align test boundaries with functional blocks for meaningful results
Feedback loop breaking: Include mechanisms to open feedback loops during testing
Analog/digital boundaries: Clearly define and provide access to mixed-signal interfaces
Hierarchical testing: Enable testing at multiple levels from component to system

Overhead Considerations

BIST circuitry impacts the primary design:

Area overhead: Test signal generators, response analyzers, and control logic consume silicon area
Performance impact: Test multiplexers and routing add parasitic loading to sensitive nodes
Power consumption: BIST circuits draw power even in normal operation unless carefully power-gated
Design complexity: Additional circuitry increases design and verification effort

The overhead must be justified by reduced external test costs, improved field diagnostics, or enhanced reliability. Typical area overhead ranges from 5% to 15% for comprehensive analog BIST.

Applications and Case Studies

Analog BIST has found application in various domains, each with specific requirements and implementation approaches.

Data Converter BIST

ADCs and DACs commonly incorporate self-test capabilities:

INL/DNL testing: On-chip ramp generation and histogram analysis for linearity measurement
SNDR testing: Sinusoidal stimulus and FFT analysis for dynamic performance
Missing code detection: Verify all codes are reachable and monotonicity is maintained
Self-calibration: Automatic adjustment of trim elements to optimize performance

Automotive Electronics BIST

Safety-critical automotive applications demand comprehensive self-test:

ISO 26262 compliance: Functional safety standards require fault detection capabilities
Power-on self-test: Verify circuit functionality before enabling safety-critical functions
Continuous monitoring: Runtime checking detects failures during operation
Redundancy management: Detect failures and switch to backup circuits

Sensor Interface BIST

Analog front-ends for sensors benefit from self-test:

Sensor connectivity testing: Verify sensor connection by measuring expected impedance
Amplifier chain testing: Inject known signals and verify amplification through the chain
Reference verification: Confirm voltage and current references are within tolerance
Environmental compensation: Self-calibrate based on temperature and supply voltage

RF Circuit BIST

Radio frequency circuits present unique BIST challenges:

Loopback testing: Connect transmitter to receiver for system-level self-test
Power detector BIST: On-chip power detectors verify transmit power levels
Frequency synthesis testing: Verify PLL lock and frequency accuracy
Modulation quality: EVM and spectral mask compliance verification

Challenges and Future Directions

Despite significant progress, analog BIST continues to present challenges that drive ongoing research and development.

Current Challenges

Key issues in analog BIST implementation:

Fault coverage uncertainty: Unlike digital circuits, analog fault coverage is difficult to quantify precisely
Test quality versus overhead tradeoff: Higher quality testing requires more complex BIST circuitry
Performance impact: BIST circuitry can degrade the analog performance being tested
Standardization: Lack of industry-wide standards complicates tool support and methodology sharing

Emerging Approaches

New techniques addressing analog BIST limitations:

Machine learning-based testing: Train classifiers on production data to improve fault detection with minimal test content
Statistical learning methods: Use population statistics to optimize test content and limits
Specification-driven BIST: Generate BIST structures automatically from specification requirements
System-level BIST: Test analog circuits within their system context rather than in isolation

Integration with Digital BIST

Unified approaches for mixed-signal testing:

Shared infrastructure: Leverage digital BIST scan chains and controllers for analog test data transport
IEEE 1149.4 mixed-signal test bus: Standard interface for analog boundary scan
Unified fault models: Develop comprehensive fault models spanning digital and analog domains
Hierarchical BIST: Coordinate digital and analog BIST for efficient system-level testing