Electronics Guide

Fixture Construction

A typical bed-of-nails fixture consists of several key components:

• Probe plate - A precisely drilled plate holding spring-loaded probes in positions corresponding to test points on the PCB
• Wiring harness - Connections from probes to the test system interface, often using wire-wrap or ribbon cable assemblies
• Vacuum or mechanical hold-down - Systems to press the board firmly against the probes for reliable contact
• Receiver plate - A guide structure ensuring proper alignment of the board with the probe array
• Support structure - A rigid frame maintaining probe positions and fixture geometry

Probe Technologies

Spring-loaded probes come in various styles suited to different applications:

• Standard crowned tips - General-purpose probes for plated through-holes and test pads
• Spear or chisel tips - Designed to penetrate oxidation or flux residue on component leads
• Cup or tulip tips - Concave tips that center on spherical contacts such as solder balls
• Blade or knife tips - For contacting fine-pitch component leads
• Serrated tips - Multiple contact points for improved reliability on contaminated surfaces

Probe selection depends on the contact surface, required current capacity, contact resistance specifications, and cycle life expectations. High-performance probes may achieve over one million cycles before requiring replacement.

Design Considerations

Successful fixture design requires careful attention to several factors:

• Test point accessibility - Ensuring adequate clearance around test points for probe placement
• Probe spacing - Maintaining minimum pitch between probes to prevent short circuits and mechanical interference
• Board support - Preventing flexing during probe contact, especially for thin or large boards
• Thermal management - Accommodating board warpage and probe expansion during powered testing
• Maintenance access - Enabling easy replacement of worn or damaged probes

In-Circuit Measurement and Vectorless Techniques

The fixture is only the access mechanism; the in-circuit tester that drives it applies several measurement techniques through those probes:

• Analog in-circuit measurement - Measuring the value of an individual resistor, capacitor, or inductor while it is soldered in the assembly, using guarding to null out parallel current paths so the component can be read in isolation
• Digital in-circuit test - Briefly back-driving device inputs to a known state and verifying outputs, confirming that logic devices are present, correctly oriented, and properly connected
• Vectorless opens testing - Detecting open connections on connectors and complex packages by capacitively coupling to a device lead frame through a sense plate, without requiring the device to be powered or functional, reaching joints that carry no simple electrical test path
• Shorts and opens screening - Rapid continuity checks across nets, which typically account for the largest single share of assembly defects

Where fixture cost or lead time is prohibitive, as with prototypes, low volumes, and high-mix production, a flying-probe tester offers a fixtureless alternative. Two or more motorized probes step from test point to test point under program control, trading throughput for the elimination of fixture tooling and its non-recurring engineering cost.

Architecture and Operation

Boundary scan architecture includes several key elements:

• Test Access Port (TAP) - A four or five wire interface (TCK, TMS, TDI, TDO, and optional TRST) providing access to on-chip test logic
• TAP Controller - A sixteen-state finite state machine, clocked by TCK and navigated by the TMS line, that sequences the capture, shift, and update operations on the scan registers
• Boundary scan register - A shift register with cells at each device pin, allowing capture and control of pin states
• Instruction register - Controls the operation mode of the boundary scan logic
• Data registers - Store test patterns and captured results

Test Capabilities

Boundary scan enables several types of testing:

• Interconnect testing - Detecting opens, shorts, and stuck-at faults between devices on the board
• Cluster testing - Testing non-boundary scan devices through boundary scan capable neighbors
• In-system programming - Programming flash memory, CPLDs, and FPGAs through the JTAG interface
• Functional testing - Applying test vectors and capturing responses at device boundaries
• Debug access - Providing on-chip debug capabilities through the JTAG interface

Implementation Benefits

Boundary scan offers significant advantages in modern electronics manufacturing:

• Reduced fixture complexity - Fewer physical probes needed when using on-chip test access
• Access to hidden nodes - Testing connections under ball grid array packages and other inaccessible points
• Consistent test coverage - Standardized methodology across different board designs
• Defect isolation - Precise identification of fault locations for efficient repair
• Design reuse - Test programs portable across product variants sharing boundary scan devices

The IEEE 1149 Standards Family

The original digital standard has grown into a family that extends boundary scan to signal types and packaging it could not originally reach:

• IEEE 1149.1 - The foundational Standard Test Access Port and Boundary-Scan Architecture, covering digital interconnect on static nets
• IEEE 1149.4 - A mixed-signal extension that adds an analog test bus, the AT1 and AT2 pins, so that analog nets and passive components can be measured through the TAP
• IEEE 1149.6 - An extension for AC-coupled and differential nets, enabling test of high-speed serial links such as LVDS that ordinary boundary scan cannot drive statically
• IEEE 1149.7 - A reduced-pin-count, two-wire test interface, known as compact JTAG, aimed at systems-on-chip, stacked die, and system-in-package assemblies
• IEEE 1687 - Known as IJTAG, this standard formalizes access to the embedded instruments and built-in self-test engines increasingly designed into modern devices

Test Strategy Development

Creating an effective functional test strategy involves several steps:

• Requirement analysis - Identifying critical functions and performance parameters that must be verified
• Test case definition - Developing specific test conditions and expected results for each requirement
• Stimulus and measurement planning - Determining the signals and measurements needed to exercise and verify each function
• Pass/fail criteria - Establishing quantitative limits for each measurement based on specifications and manufacturing capability
• Test sequence optimization - Ordering tests to minimize total test time while maintaining effective screening

Test System Architecture

Functional test systems typically include:

• Signal generators - Providing stimulus signals such as DC power, RF signals, digital patterns, or analog waveforms
• Measurement instruments - Capturing device responses including voltages, currents, timing, frequencies, and power levels
• Switching matrices - Routing signals between instruments and multiple test points on the device
• Load simulation - Representing actual operating conditions including resistive, capacitive, and active loads
• Test executive software - Coordinating test sequences, collecting data, and making pass/fail decisions

Test Program Development

Effective test program development follows established practices:

• Modular test architecture - Creating reusable test modules that can be combined for different product configurations
• Parameterized testing - Using configuration files to adapt test programs to product variants
• Error handling - Implementing robust exception handling to maintain system stability
• Data logging - Recording comprehensive test data for traceability and analysis
• Operator interface - Providing clear guidance for test operators and technicians

Stress Conditions

Common stress parameters used in burn-in include:

• Elevated temperature - Operating devices above normal ambient, typically 85 to 125 degrees Celsius
• Temperature cycling - Repeatedly transitioning between temperature extremes to stress solder joints and material interfaces
• Elevated voltage - Operating at voltages above nominal to accelerate voltage-dependent failure mechanisms
• Power cycling - Repeatedly powering devices on and off to stress power-on transients
• Vibration - Applying mechanical stress to identify marginal connections

Burn-in System Components

A complete burn-in system includes:

• Environmental chambers - Controlled temperature and humidity enclosures accommodating multiple units under test
• Burn-in boards - Carrier boards providing power and signal connections to devices within the chamber
• Power distribution - Systems delivering stable power to many devices simultaneously
• Monitoring systems - Continuous or periodic testing to detect failures during burn-in
• Data collection - Recording device responses and failure data for reliability analysis

Dynamic versus Static Burn-in

Burn-in approaches differ in how devices are exercised during stress:

• Static burn-in - Devices are powered but not actively exercised, primarily screening for temperature-related failures
• Dynamic burn-in - Devices execute test patterns during stress, enabling detection of functional failures and improving coverage of complex ICs
• Monitored burn-in - Combines dynamic operation with continuous or periodic testing to detect exactly when failures occur

Acceleration, Duration, and Cost

Because most temperature-activated failure mechanisms follow an Arrhenius relationship, raising temperature accelerates aging exponentially, allowing a screen of hours to represent a much longer period of field operation. Engineers choose the time-and-temperature profile to precipitate infant mortality without consuming meaningful useful life. Burn-in is costly in capital, energy, and cycle time, so it is increasingly reserved for high-reliability applications such as automotive, aerospace, medical, and military electronics. Elsewhere, mature and well-characterized processes often justify burn-in reduction or elimination, substituting statistical screens, quiescent-current testing, and tightened parametric limits once field data confirm a low defect rate.

Key Parameters

Common parametric measurements include:

• DC parameters - Supply current, input/output voltage levels, leakage currents, and threshold voltages
• AC parameters - Propagation delays, setup and hold times, rise and fall times, and maximum operating frequency
• Analog parameters - Gain, bandwidth, offset, linearity, and noise characteristics
• Power parameters - Static and dynamic power consumption, power supply rejection, and thermal characteristics
• RF parameters - Frequency accuracy, output power, sensitivity, and spurious emissions

Measurement Techniques

Accurate parametric measurements require attention to:

• Force and measure methodology - Applying precise stimulus while measuring device response
• Kelvin sensing - Using separate force and sense connections to eliminate lead resistance errors
• Guard techniques - Preventing leakage currents from affecting high-impedance measurements
• Settling time - Allowing sufficient time for signals to stabilize before measurement
• Averaging and filtering - Reducing noise effects on measurements through statistical techniques
• Quiescent current (IDDQ) testing - Measuring the small static supply current of a CMOS device to expose manufacturing defects, such as gate-oxide shorts and bridging faults, that leave logic function intact but raise leakage

Limit Setting

Establishing appropriate test limits balances several considerations:

• Specification compliance - Ensuring tested units meet published device specifications
• Guard bands - Providing margin between test limits and specification limits to account for measurement uncertainty
• Process capability - Setting limits achievable by the manufacturing process with acceptable yield, commonly expressed through capability indices such as Cp and Cpk that compare the process spread to the width of the limit window
• Customer requirements - Meeting any application-specific requirements beyond standard specifications
• Statistical process control - Using parametric data to monitor and improve manufacturing processes

Common Yield Metrics

Several standard metrics quantify manufacturing performance and defect levels:

• First-pass yield (FPY) - The fraction of units that pass a test step on the first attempt, without rework or retest
• Rolled throughput yield (RTY) - The product of the first-pass yields across every step, expressing the probability that a unit passes the entire process untouched
• Defects per million opportunities (DPMO) - A normalized defect rate that accounts for the number of ways each unit can be defective, enabling comparison across products of differing complexity
• Test escape and false-failure rates - The proportion of defective units that pass (escapes) and of good units that fail (false rejects), which together gauge the quality of the test itself

Data Collection and Management

Effective yield analysis begins with comprehensive data collection:

• Test data aggregation - Consolidating results from multiple test stations and operations
• Traceability linking - Associating test results with lot, date, equipment, and material information
• Parametric data storage - Recording actual measured values, not just pass/fail results
• Failure mode classification - Categorizing failures by symptom, location, or root cause
• Data quality assurance - Validating data integrity and identifying anomalies in collection

Analysis Techniques

Common yield analysis methods include:

• Pareto analysis - Identifying the most significant contributors to yield loss
• Trend analysis - Tracking yield and failure rates over time to detect shifts or patterns
• Correlation analysis - Finding relationships between yield and process variables
• Distribution analysis - Characterizing the statistical distribution of parametric measurements
• Spatial analysis - Identifying patterns related to position on wafers or panels

Continuous Improvement

Yield analysis supports ongoing process improvement through:

• Root cause identification - Using data patterns to pinpoint sources of defects
• Process control feedback - Providing early warning of process drift before yield impact becomes severe
• Design feedback - Identifying design features that create manufacturing challenges
• Supplier quality management - Tracking component or material related failures back to sources
• Cost reduction - Quantifying the impact of yield improvements on manufacturing cost

Coverage Metrics

Several metrics quantify test coverage:

• Fault coverage - The percentage of possible faults detectable by the test program
• Stuck-at fault coverage - Coverage of faults where nodes are stuck at logic high or low
• Structural coverage - Percentage of physical connections and components verified
• Functional coverage - Extent to which product functions have been exercised
• Defect coverage - Estimated percentage of actual defects detected, based on defect models

Structural Defect Coverage Models

Because a single "percent coverage" figure can hide important gaps, the industry uses structured defect-spectrum models to describe exactly what a test does and does not detect. The most widely adopted, pioneered by Agilent in the 1990s and later extended by iNEMI, is the PCOLA/SOQ/FAM model:

• PCOLA (component coverage) - Presence, Correctness, Orientation, Liveness, and Alignment, describing whether each component is there, is the right part, faces the right way, functions, and sits within placement tolerance
• SOQ (connection coverage) - Shorts, Opens, and Quality, describing coverage of the solder joints and nets that tie components together
• FAM (functional coverage) - Feature, At-speed, and Measurement, the iNEMI additions that credit functional testing for exercising features, doing so at operating speed, and taking real parametric measurements

Scoring each attribute per component and per net makes coverage gaps explicit and lets engineers see how the in-circuit, boundary scan, and functional stages complement one another across the full fault spectrum, rather than reducing test quality to a single number.

Coverage Analysis Methods

Tools and techniques for analyzing test coverage include:

• Fault simulation - Modeling faults in circuit descriptions and simulating test detection
• Design for Test analysis - Evaluating testability features during design phase
• Test point analysis - Determining accessibility of circuit nodes for probing
• Automatic test pattern generation - Creating test vectors optimized for fault detection
• Coverage gap identification - Finding untested areas requiring additional test development

Optimization Strategies

Improving test coverage while managing costs requires strategic approaches:

• Multi-strategy testing - Combining in-circuit, boundary scan, and functional testing for complementary coverage
• Defect-based prioritization - Focusing test development on the most likely and impactful defect types
• Test time reduction - Eliminating redundant tests and optimizing measurement sequences
• Design for testability - Incorporating test access points and built-in test features during product design
• Adaptive testing - Adjusting test depth based on product history or incoming quality indicators