FPGA and Programmable Logic Development

Field-programmable gate arrays (FPGAs) and other programmable logic devices provide a flexible platform for implementing custom digital logic without the time and expense of fabricating an application-specific integrated circuit (ASIC). Because their internal logic and routing are configured after manufacture—and, in the case of SRAM-based FPGAs, reconfigured every time the device powers up—these parts let a team build, test, and revise hardware in hours rather than the months and millions of dollars an ASIC tape-out demands. That agility makes them a natural fit for prototyping, low-to-medium-volume production, algorithm acceleration, and any design that must adapt to changing requirements or evolving standards.

This category covers the tools, boards, and methodologies used to design, simulate, and deploy programmable logic, from hardware description languages and synthesis software through development boards and on-chip debugging. The subcategories below progress from accessible learning platforms toward professional systems, and from low-level register-transfer design toward high-level synthesis that compiles software languages into hardware.

Subcategories

CPLD Development Platforms — Development resources for complex programmable logic devices (CPLDs), including AMD (Xilinx) CoolRunner-II and Altera MAX series parts, low-power and non-volatile platforms, glue-logic and legacy-system interfacing, simple state-machine implementation, and educational CPLD kits.
Entry-Level FPGA Boards — Affordable boards for learning and experimentation, including Lattice iCE40 and ECP5 platforms well suited to open-source toolchains, Digilent educational kits, Terasic DE-series boards, and open-hardware projects aimed at students and hobbyists.
HDL Development Tools and Simulators — Hardware description language environments and verification tools, including AMD Vivado Design Suite, Altera Quartus Prime, Siemens EDA ModelSim and Questa, the open-source Yosys and nextpnr flow, SystemVerilog and VHDL toolchains, and waveform viewers.
High-Level Synthesis Platforms — Tools that raise the design abstraction by compiling C, C++, and other high-level languages into hardware, including AMD Vitis HLS, the Altera HLS Compiler, MATLAB and Simulink HDL Coder, Python-based hardware generators, and algorithm-acceleration frameworks.
Professional FPGA Development Systems — Advanced platforms for production hardware development, including AMD Kintex, Virtex, and Versal evaluation boards, Altera Agilex and Stratix kits, high-speed transceiver and DSP development, hardware-acceleration platforms, partial reconfiguration, and system-on-chip prototyping.

How FPGA Development Differs

FPGA development blends the mindset of hardware design with the iterative rhythm of software work, and the combination trips up newcomers from either background. A design is described in a hardware description language such as VHDL or SystemVerilog, but that description does not run instruction by instruction. It defines logic that exists all at once and operates in parallel, so the engineer reasons about concurrent signals, clock domains, and the propagation delay between registers rather than about a sequence of executed statements.

Two constraints dominate the work. The first is timing: every path between flip-flops must settle within a clock period, and the tools verify this through static timing analysis against the constraints the designer supplies. A design that is logically correct can still fail because a path is too slow. The second is resource utilization, the finite budget of look-up tables, flip-flops, block RAM, and dedicated DSP slices on a given device. Trading one resource for another—say, using a multiplier block instead of building one from logic fabric—is a routine part of meeting both timing and capacity targets.

The build itself is a multi-stage pipeline rather than a compile. Synthesis converts HDL into a netlist of primitives; placement and routing map that netlist onto the physical device; and a final step generates the configuration bitstream loaded into the FPGA. Each stage can take minutes on a small device and hours on a large one, which is why simulation and verification are central to the discipline. Catching a bug in a testbench is far cheaper than discovering it after a long place-and-route run on real hardware.

The Vendor and Tool Landscape

The programmable logic market is dominated by two suppliers, joined by a strong specialist and a maturing open-source movement. Each vendor pairs its silicon with a proprietary toolchain, and choosing a device usually means committing to that vendor's software for the life of the design.

AMD (formerly Xilinx)

AMD, which acquired Xilinx in 2022, supplies the Spartan and Artix value families, the Kintex and Virtex performance families, and the Versal adaptive system-on-chip platform that integrates programmable logic with Arm processors and AI engines. Its primary design tool is the Vivado Design Suite, with the broader Vitis platform layering software development and high-level synthesis (Vitis HLS) on top of Vivado.

Altera (formerly Intel's programmable solutions group)

Altera, spun out as an independent company in 2025 after a period as Intel's programmable solutions group, offers the Cyclone, Arria, and Stratix families along with the newer Agilex line. Its design environment is Quartus Prime, complemented by an HLS compiler for C-based hardware development. Designs created during the Intel era carry forward, but new work increasingly appears under the renewed Altera identity.

Lattice and low-power specialists

Lattice Semiconductor concentrates on small, low-power devices rather than competing at the high end. Its iCE40 family includes some of the smallest FPGAs available, well suited to wearables and always-on sensing, while the ECP5 family offers more capacity for cost-sensitive mid-range designs. These parts are popular in education and among hobbyists precisely because they are inexpensive and well documented.

Open-source toolchains

A community-driven flow has matured into a practical alternative for supported devices. Yosys performs synthesis, nextpnr handles placement and routing, and device-specific projects such as Project IceStorm document the bitstream format. The flow targets Lattice iCE40 and ECP5 parts most completely, with broader device support under active development. For verification, the open-source Verilator simulator compiles HDL into fast C++ models. These tools lower the barrier to entry, run on modest hardware, and make the full build process inspectable, though they do not yet match the device coverage or polish of the vendor suites.

Choosing a Development Path

Selecting tools and a board follows from the goal. A student or hobbyist learning digital design is best served by an inexpensive entry-level board paired with either a free vendor edition or the open-source flow, where fast iteration matters more than raw capacity. An engineer prototyping a product chooses a device family by gate count, transceiver speed, and on-chip resources, then accepts the corresponding professional toolchain and an evaluation board that mirrors the target hardware.

The choice between register-transfer design and high-level synthesis is equally consequential. Hand-written HDL gives precise control over timing and resources and remains the norm for interfaces, control logic, and area-critical blocks. High-level synthesis trades some of that control for productivity, letting teams explore algorithm-heavy designs—signal processing, machine-learning inference, video pipelines—in C or C++ and generate competitive hardware far faster than coding it by hand. Many real projects combine both, writing critical paths in HDL and accelerating compute-bound kernels through synthesis. Understanding these trade-offs, and the strengths of each vendor and tool, lets a developer match the platform to the problem. The subcategories above examine each in detail.