Electronics Guide

Hierarchical Floor Planning

Hierarchical floor planning partitions complex designs into manageable blocks that can be implemented independently before integration:

• Block partitioning: Dividing the design into logical functional units based on hierarchy, function, or timing domains.
• Aspect ratio selection: Choosing block dimensions that balance internal routing efficiency with global interconnect requirements.
• Block placement: Positioning blocks to minimize critical path lengths and reduce congestion at block boundaries.
• Interface planning: Defining pin locations at block boundaries to optimize inter-block routing.
• Hard macro integration: Incorporating memory blocks, analog circuits, and IP cores with fixed layouts.

Hierarchical approaches enable parallel implementation of blocks, reduce tool runtime, and provide tighter control over critical interfaces.

Flat Floor Planning

Flat floor planning treats the entire design as a single entity, allowing the tools maximum flexibility in cell placement:

• Global optimization: Tools can optimize across the entire design without artificial block boundaries.
• Simplified methodology: Eliminates the need to define block interfaces and pin assignments.
• Suited to smaller designs: Most effective when design size is within current tool capacity.
• Timing optimization: Critical paths can be optimized without block boundary constraints.

Flat implementation works well for designs up to roughly several million instances, a threshold that continues to rise as tool capacity and compute resources grow.

I/O and Pad Planning

I/O planning establishes the locations of input and output structures that connect the chip to the external world:

• Pad ring organization: Arranging I/O pads around the chip periphery or in area-I/O (flip-chip) configurations.
• Signal grouping: Clustering related signals, such as buses and differential pairs, to simplify package and board routing.
• Power pad distribution: Placing power and ground pads to ensure adequate current delivery throughout the ring.
• ESD structure placement: Integrating electrostatic-discharge protection at each I/O location.
• Package compatibility: Aligning pad locations with package pin maps and bonding or bump requirements.

Timing-Driven Floor Planning

Timing-driven floor planning uses timing constraints to guide block placement decisions:

• Critical path analysis: Identifying timing-critical nets that require short physical paths.
• Affinity-based placement: Positioning blocks with high connectivity close together.
• Latency budgeting: Allocating timing margins across block boundaries based on path requirements.
• Pipeline insertion points: Planning register locations to balance pipeline stages.
• Clock domain separation: Organizing the floor plan to group synchronous logic and minimize clock domain crossings.

Power Grid Architecture

The power distribution network typically employs a hierarchical mesh structure:

• Top-level straps: Wide metal on upper layers providing low-resistance delivery from pads or bumps to the core.
• Power rings: Continuous metal loops around the chip periphery or block boundaries collecting power from the supply.
• Power stripes: Regularly spaced vertical and horizontal traces distributing power across the core area.
• Standard cell rails: Fine-pitch power and ground traces in lower metal layers directly feeding standard cells.
• Via stacks: Vertical connections linking power structures across metal layers.

The mesh structure provides redundant current paths, reducing the impact of manufacturing defects and promoting uniform voltage distribution.

IR Drop Analysis and Mitigation

IR drop occurs when current flowing through resistive power-grid elements causes a voltage reduction:

• Static IR drop: Voltage drop due to average DC current, analyzed with average power estimates.
• Dynamic IR drop: Transient voltage variation caused by switching activity, requiring vector-based or vectorless simulation.
• Worst-case analysis: Identifying the current scenarios that produce the largest voltage drops.
• Hot spot identification: Locating regions where IR drop exceeds acceptable limits.

Mitigation strategies include adding power straps, widening existing traces, increasing via density, and redistributing high-power cells.

Electromigration Considerations

Electromigration is the gradual displacement of metal atoms driven by momentum transfer from the electron current, eventually causing opens or shorts:

• Current density limits: Each metal layer has a maximum allowable current density that depends on wire width and temperature.
• Average, RMS, and peak current: Average current drives material transport, while RMS and peak currents drive self-heating; all contribute to electromigration stress.
• Temperature dependence: Electromigration accelerates strongly with temperature, following an Arrhenius relationship.
• Wire sizing: Power-grid elements must be sized to keep current density within safe limits.
• Via redundancy: Multiple parallel vias reduce the current density through each individual via.

Power-grid design must account for electromigration to ensure reliability over the product lifetime, often specified as ten years or more.

Multi-Voltage Domain Design

Modern systems on chip employ multiple voltage domains to optimize power consumption:

• Voltage areas: Regions operating at different supply voltages, each requiring independent power distribution.
• Level shifters: Interface cells that translate signals between voltage domains, placed at domain boundaries.
• Power switches: Header or footer transistors that disconnect power to idle blocks, requiring careful placement and routing.
• Isolation cells: Cells that clamp the outputs of powered-down blocks so they do not corrupt active logic.
• Always-on logic: Retention registers and control logic that remain powered during low-power states, requiring a robust independent supply.

These intentions are commonly captured in a power-intent file using the IEEE 1801 Unified Power Format (UPF), which the implementation and verification tools read to insert and check the required cells.

Decoupling Capacitor Insertion

Decoupling capacitors provide local charge storage to maintain a stable supply during transient current demands:

• Placement strategy: Distributing decaps throughout the design, concentrated near high-switching-activity regions.
• Capacitor types: Standard-cell decaps, filler cells with capacitance, and dedicated capacitor structures.
• Frequency response: Different capacitor sizes provide effective decoupling at different frequencies.
• Area trade-offs: Balancing decap area against functional-cell area and routing resources, and managing the leakage that thin-oxide decaps add.
• Automatic insertion: Tools can place decaps in available whitespace after placement.

Clock Tree Topologies

Several fundamental topologies serve different design requirements:

• H-tree: A symmetric branching structure that provides inherently balanced delays to all endpoints.
• Fishbone: A central spine with lateral branches, efficient for elongated floorplans.
• Mesh or grid: A grid of interconnected clock wires driven by many distributed buffers, providing redundancy and very low skew, common in high-performance processors.
• Conventional buffered tree: An automatically synthesized tree of buffers and inverters, the default for most application-specific integrated circuits (ASICs).
• Hybrid: A combination of topologies, often using a mesh or spine at the top level with buffered trees locally.

The optimal topology depends on die size, clock frequency, skew requirements, and power constraints.

Skew and Latency Management

Clock skew is the variation in clock arrival times at different sequential elements:

• Local skew: The difference in clock arrival between launch and capture registers of a path, which directly affects setup and hold timing.
• Global skew: The maximum difference across all clock endpoints, used in worst-case analysis.
• Insertion delay (latency): The total delay from the clock source to the endpoints, which the tool keeps bounded.
• Useful skew: Skew intentionally introduced to borrow time and help meet timing on critical paths.
• On-chip variation (OCV): Manufacturing and environmental variation that affects skew and is modeled with derates during analysis.

CTS tools balance clock paths by inserting buffers, adjusting wire lengths, and using delay cells to reach target skew and latency values.

Buffer Insertion and Sizing

Clock buffers drive capacitive loads while maintaining signal integrity:

• Buffer tree construction: Building hierarchical buffer chains to drive the clock load.
• Buffer sizing: Selecting drive strengths that balance delay, power, and transition (slew) time.
• Inverter pairs: Using pairs of inverters rather than buffers, which can improve duty-cycle and transition symmetry.
• Integrated clock-gating cells: Cells that combine an enable with the clock buffer to gate the clock.
• Low-skew buffers: Specialized cells with matched rise and fall delays for critical clock paths.

Clock Gating Implementation

Clock gating reduces dynamic power by stopping the clock to inactive logic:

• RTL-level gating: Architectural clock enables identified during synthesis.
• Sequential clock gating: Inserting clock gates automatically where register inputs are known to be stable.
• Hierarchical gating: A multi-level gating structure with coarse and fine-grained control.
• Gating cell placement: Positioning clock gates to minimize their impact on clock-tree balance.
• Enable timing: Ensuring gating signals settle before the clock edge to prevent glitches.

Multi-Clock Domain Handling

Complex systems on chip contain multiple clock domains that require coordinated distribution:

• Independent trees: Separate clock trees for each domain with no shared buffering.
• Derived clocks: Clocks generated by dividers or PLLs from a common source.
• Clock domain crossing: Synchronizers at domain boundaries that require controlled clock relationships.
• Concurrent optimization: Balancing multiple clock trees together for a consistent methodology.
• Asynchronous interfaces: Handling communication between unrelated clock domains.

Global Placement

Global placement establishes approximate cell locations across the entire chip:

• Analytical placement: Formulating placement as a continuous optimization problem that minimizes a wirelength cost function.
• Quadratic placement: Using a quadratic wirelength model that admits efficient solution by solving linear systems.
• Force-directed methods: Modeling nets as springs that pull connected cells together, with spreading forces that reduce overlap.
• Partition-based methods: Recursively dividing the netlist and chip area into smaller subproblems.
• Simulated annealing: Probabilistic optimization that accepts temporarily worse solutions to escape local minima, now used mainly for macros or small problems.

Most contemporary tools use analytical global placement, producing an initial solution that detailed placement then refines.

Detailed Placement

Detailed placement legalizes and refines cell positions onto legal row and site locations:

• Legalization: Snapping cells to legal sites and eliminating overlaps with minimal displacement.
• Cell spreading: Distributing cells to avoid local density hot spots.
• Local optimization: Swapping or shifting adjacent cells to reduce local wirelength.
• Cell flipping: Mirroring cells so that abutting power rails align and routing conflicts decrease.
• Incremental improvement: Iteratively refining placement through local moves.

Timing-Driven Placement

Timing-driven placement prioritizes meeting timing constraints:

• Net weighting: Assigning higher weights to timing-critical nets to pull their cells closer.
• Path-based optimization: Analyzing complete timing paths rather than individual nets.
• Slack distribution: Allocating timing slack across path segments according to criticality.
• Concurrent timing analysis: Updating timing during placement iterations for accurate guidance.
• Timing-driven legalization: Prioritizing timing over wirelength during detailed placement.

Congestion-Aware Placement

Congestion-aware placement anticipates routing-resource limitations:

• Congestion estimation: Predicting routing demand from cell connectivity and locations, often using a fast global-route estimate.
• Density control: Limiting local cell density to reserve routing resources.
• Congestion-driven spreading: Dispersing cells away from high-congestion regions.
• Pin density management: Avoiding excessive pin concentration in local areas.
• Routing layer awareness: Considering the resources available on each metal layer.

Macro Placement

Macro placement handles large fixed-size blocks such as memories and IP cores:

• Channel planning: Leaving routing channels between macros for signal paths.
• Orientation optimization: Selecting macro orientations that minimize pin-to-logic distances.
• Clustering: Grouping related macros, such as the banks of a memory array, for efficient connectivity.
• Halo and keep-out regions: Defining placement and routing blockages around macros.
• Abutment: Placing compatible macros edge to edge to share power rails or signals.

Global Routing

Global routing assigns nets to routing regions without determining exact paths:

• Routing graph construction: Building a coarse grid of global routing cells (g-cells) and their edge capacities.
• Path assignment: Finding a route for each net through the routing graph.
• Congestion management: Balancing demand across regions to avoid exceeding capacity (overflow).
• Layer assignment: Determining which metal layers carry each net segment.
• Rip-up and reroute: Iteratively removing and re-routing nets that cause congestion or timing violations.

Global routing produces a plan that guides detailed routing while exposing potential congestion problems early.

Detailed Routing

Detailed routing creates the actual metal and via geometry:

• Track assignment: Assigning wire segments to specific routing tracks.
• Design rule compliance: Satisfying spacing, width, minimum-area, and via rules.
• Via optimization: Minimizing via count while maintaining connectivity.
• Metal fill: Adding non-functional fill metal to satisfy density requirements for planarization.
• Antenna fixing: Adding antenna diodes or layer jumps to limit charge accumulation that could damage gate oxide during plasma processing.

Layer Assignment Strategies

Effective layer assignment improves routing efficiency and signal integrity:

• Preferred direction: Routing horizontally on some layers and vertically on others to reduce via count.
• Layer characteristics: Assigning fast or long nets to thicker, lower-resistance upper-metal layers.
• Power routing: Reserving thick upper metals for power distribution.
• Signal separation: Isolating sensitive analog signals from noisy digital nets.
• Clock routing: Using preferred layers and shielding for clock distribution.

Via Optimization

Vias connect different metal layers but add resistance and manufacturing risk:

• Via minimization: Reducing via count through better layer assignment.
• Multi-cut vias: Using parallel via cuts for lower resistance and better reliability.
• Via enclosure: Ensuring adequate metal overlap around vias as required by design rules.
• Via stacking: Aligning vias vertically when connecting across multiple layers.
• Post-route via repair: Inserting redundant vias after routing to improve yield and reliability.

Special Net Routing

Certain nets require special routing treatment:

• Clock nets: Balanced routing with matched delays, often on preferred layers with shielding.
• High-speed buses: Length-matched routing for timing-critical parallel signals.
• Differential pairs: Closely coupled traces maintaining controlled impedance and matching.
• Power nets: Wide, low-resistance straps that follow the power-grid plan.
• Shielded nets: Sensitive signals protected by grounded guard traces to limit crosstalk.

Congestion Metrics

Quantifying congestion guides optimization effort:

• Horizontal and vertical overflow: The number of routing tracks demanded beyond the available capacity.
• Global routing congestion: Congestion measured on the global-routing graph.
• Local density: Pin and cell concentration in small regions.
• Layer utilization: The percentage of available tracks used on each metal layer.
• Hot spot identification: Locating the regions that need focused optimization.

Congestion Visualization

Visualization helps engineers understand congestion patterns:

• Congestion maps: Color-coded displays showing congestion levels across the die.
• Layer-by-layer views: Examining congestion on individual routing layers.
• Pin density plots: Identifying regions with excessive pin concentration.
• Route path display: Visualizing actual routes to understand the causes of congestion.
• Trend analysis: Tracking congestion changes across iterations.

Congestion Relief Techniques

Several approaches address routing congestion:

• Cell spreading: Redistributing cells to reduce local density.
• Blockage insertion: Adding placement blockages to steer cells away from congested areas.
• Channel widening: Increasing spacing between macros to provide more routing resources.
• Pin swapping: Exchanging logically equivalent pins to relieve local congestion.
• Gate cloning: Duplicating high-fanout drivers to split routing demand.
• Layer promotion: Moving congested nets to less-utilized layers.

Design-Level Congestion Solutions

Sometimes congestion requires design or methodology changes:

• Hierarchy restructuring: Reorganizing the design hierarchy to improve connectivity.
• Floor plan adjustment: Repositioning blocks to create better routing channels.
• Logic restructuring: Modifying RTL to reduce high-fanout nets or bus widths.
• Metal layer addition: Adding routing layers when the technology and budget permit.
• Die size increase: Expanding the available area when congestion is fundamental.

Timing Analysis Integration

Timing analysis is embedded throughout the P&R flow:

• In-flow timing: Continuous timing updates as placement and routing progress.
• Incremental timing: Efficient updates that recompute only the affected paths.
• Path-based analysis: Considering complete timing paths rather than individual gates.
• Multi-corner analysis: Optimizing across process, voltage, and temperature corners.
• Statistical and parametric timing: Accounting for manufacturing variation probabilistically.

Setup Optimization Techniques

Setup violations require reducing path delay. Tools apply several transformations:

• Buffer insertion: Adding buffers on long nets to reduce delay and restore signal transitions.
• Gate sizing: Increasing the drive strength of cells on critical paths.
• Threshold-voltage swapping: Substituting faster, higher-leakage low-Vt cells where timing requires.
• Logic restructuring and pin swapping: Reducing critical-path depth or moving a late signal to a faster pin.
• Net topology and layer optimization: Restructuring Steiner trees and promoting critical nets to faster layers.
• Useful skew: Adjusting clock arrival times to borrow time across stages.

Hold Time Fixing

Hold violations occur when data arrives too quickly at the capture register:

• Delay buffer and delay-cell insertion: Adding cells that lengthen fast paths in a controlled way.
• Path detour: Lengthening wire paths to add delay where buffers are undesirable.
• Clock skew adjustment: Adjusting clock arrival to restore hold margin.
• Post-CTS fixing: Most hold fixing is done after clock tree synthesis, once clock skew is known, and is rechecked after routing.

Hold fixing must avoid degrading setup margin, so tools balance the two and avoid over-padding paths.

Multi-Mode Multi-Corner Optimization

A design must meet timing across all operating conditions and modes:

• Process corners: Fast, typical, and slow transistor characteristics.
• Voltage corners: Nominal and reduced supply voltages.
• Temperature corners: The extremes of the operating temperature range.
• Functional modes: Different clock frequencies or operational states, including test modes.
• Concurrent optimization: Closing all relevant mode and corner scenarios together rather than sequentially.

Closure Methodology

Systematic approaches improve closure efficiency:

• Incremental flows: Building on previous results rather than restarting from scratch.
• Convergent optimization: Ensuring each iteration makes net progress toward closure.
• Priority-based fixing: Addressing the worst violations first.
• Margin management: Trading timing margin for other objectives as closure progresses.
• Checkpoint strategy: Saving intermediate results to recover from failed experiments.

Post-Route Optimization

Fine-tuning after routing completes:

• In-place optimization: Improving cells without significantly changing their locations.
• Wire optimization: Adjusting routes for better timing or integrity.
• Via optimization: Adding redundant vias or refining via positions.
• Final buffer insertion: Adding buffers where final timing analysis shows they are needed.
• Leakage recovery: Swapping non-critical cells to higher-threshold, lower-leakage variants.

Signoff Timing Closure

Final timing is confirmed under signoff conditions, typically using dedicated signoff tools rather than the implementation engine:

• Signoff-quality extraction: Using accurate parasitic extraction for final timing.
• Advanced OCV: Applying on-chip-variation derates for realistic worst-case analysis.
• AOCV and POCV: Advanced or parametric on-chip variation for more accurate variation modeling.
• IR-drop-aware timing: Accounting for the effect of voltage drop on cell delay.
• Noise-aware timing: Including crosstalk-induced delay and noise in the analysis.

Physical Verification Closure

Physical verification confirms the layout meets all manufacturing requirements:

• Design rule checking (DRC): Verifying that all geometric rules are satisfied.
• Layout versus schematic (LVS): Confirming the layout connectivity matches the netlist.
• Antenna checking: Ensuring plasma processing cannot damage gate oxide.
• Density checking: Verifying metal and other layer densities meet manufacturing limits.
• Electrical rule checking (ERC): Validating power connectivity and electrical constraints.

Types of ECOs

Different ECO types call for different implementation approaches:

• Functional ECOs: Logic changes that fix bugs or add functionality.
• Timing ECOs: Modifications that fix timing violations.
• Power ECOs: Changes that reduce power consumption.
• Metal-only ECOs: Changes confined to routing and via layers, preserving the transistor (base) layers.
• Pre-mask versus post-mask ECOs: Changes made before tape-out are unrestricted, while post-mask changes are constrained to spare resources.

ECO Methodology

Systematic ECO implementation minimizes risk and effort:

• Change isolation: Limiting the ECO scope to minimize ripple effects.
• Spare cell utilization: Mapping functional changes onto pre-placed spare gates.
• Incremental placement: Placing new cells with minimal disturbance to the existing layout.
• Incremental routing: Routing ECO nets while preserving existing routes.
• Targeted verification: Focusing verification on the changed regions.

Spare Cell Strategies

Spare cells facilitate post-mask modifications:

• Spare cell types: A variety of gates (NAND, NOR, inverters, flip-flops) distributed throughout the design.
• Distribution strategy: Placing spare cells uniformly or concentrating them near likely change areas.
• Spare cell connection: Pre-connecting power and ground while leaving signal pins available.
• Utilization tracking: Monitoring spare-cell usage across ECO iterations.
• Gate-array filler cells: Reconfigurable filler cells whose function is set by metal layers, an alternative to discrete spare gates.

Metal-Only ECOs

Metal-only ECOs modify routing without changing the transistor layers:

• Cost advantages: Only the changed mask layers are remade, significantly reducing non-recurring engineering (NRE) cost.
• Time savings: A shorter manufacturing cycle than a full base-layer respin.
• Limitations: No new transistors can be added; changes must use existing spare or gate-array cells.
• Layer restrictions: Sometimes only specific metal layers may be modified.
• Verification requirements: The change must be verified not to disturb other aspects of the design.

ECO Verification

Thorough verification ensures ECO correctness:

• Formal equivalence: Proving the modified netlist matches the updated RTL.
• Incremental timing: Analyzing the timing impact of the change.
• Physical verification: Running DRC and LVS on the modified regions.
• Regression testing: Confirming that existing functionality is preserved.
• Change documentation: Recording all modifications for future reference.

Machine Learning in Place and Route

Machine learning is increasingly applied to physical design:

• Congestion prediction: Models that predict routing congestion before detailed routing.
• Timing prediction: Estimating post-route timing during placement.
• Parameter tuning: Automatically optimizing tool settings for a given design.
• Reinforcement-learning placement: Treating macro or block placement as a sequential decision problem, an approach published by several groups and adopted in commercial flows.
• Design space exploration: Efficiently searching large parameter spaces across many runs.

3D IC Implementation

Three-dimensional integration introduces new P&R challenges:

• Through-silicon via (TSV) planning: Placing the vertical connections between stacked die.
• Multi-die floor planning: Coordinating placement across stacked die and interposers.
• Thermal-aware placement: Managing heat dissipation in dense 3D structures.
• Inter-die routing: Optimizing signal paths across die boundaries and hybrid-bond interfaces.
• Power delivery: Distributing power through multiple die levels.

Advanced Node Challenges

Leading-edge process nodes present unique P&R challenges:

• Multiple patterning: Decomposing layouts for double, triple, or self-aligned patterning, and respecting coloring rules during routing.
• Complex design rules: Managing hundreds of context-dependent rules.
• Restricted track grids: Routing on fixed grids with limited via positions and unidirectional lower layers.
• New cell architectures: Accommodating FinFET and gate-all-around (GAA) nanosheet transistors, and emerging backside power delivery.
• Manufacturability: Ensuring layouts yield well, often through design-for-manufacturing optimization.