Electronics Guide

Hierarchical Floor Planning

Hierarchical floor planning partitions complex designs into manageable blocks that can be implemented independently before integration:

• Block partitioning: Dividing the design into logical functional units based on hierarchy, function, or timing domains
• Aspect ratio selection: Choosing block dimensions that balance internal routing efficiency with global interconnect requirements
• Block placement: Positioning blocks to minimize critical path lengths and reduce congestion at block boundaries
• Interface planning: Defining pin locations at block boundaries to optimize inter-block routing
• Hard macro integration: Incorporating memory blocks, analog circuits, and IP cores with fixed layouts

Hierarchical approaches enable parallel implementation of blocks, reduce tool runtime, and provide better control over critical interfaces.

Flat Floor Planning

Flat floor planning treats the entire design as a single entity, allowing the tools maximum flexibility in cell placement:

• Global optimization: Tools can optimize across the entire design without artificial block boundaries
• Simplified methodology: Eliminates the need to define block interfaces and pin assignments
• Better for smaller designs: Most effective when design complexity is manageable by current tool capabilities
• Timing optimization: Critical paths can be optimized without block boundary constraints

Flat implementations work well for designs under approximately 10 million gates, though this threshold continues to rise with advancing tool capabilities.

I/O and Pad Planning

I/O planning establishes the locations of input/output structures that connect the chip to the external world:

• Pad ring organization: Arranging I/O pads around the chip periphery or in area I/O configurations
• Signal grouping: Clustering related signals (buses, differential pairs) to simplify board-level routing
• Power pad distribution: Placing power and ground pads to ensure adequate current delivery throughout the I/O ring
• ESD structure placement: Integrating electrostatic discharge protection at each I/O location
• Package compatibility: Aligning pad locations with package pin maps and bonding requirements

Timing-Driven Floor Planning

Timing-driven floor planning uses timing constraints to guide block placement decisions:

• Critical path analysis: Identifying timing-critical nets that require short physical paths
• Affinity-based placement: Positioning blocks with high connectivity close together
• Latency budgeting: Allocating timing margins across block boundaries based on path requirements
• Pipeline insertion points: Planning register locations to balance pipeline stages
• Clock domain separation: Organizing floor plan to group synchronous logic and minimize clock domain crossings

Power Grid Architecture

The power distribution network typically employs a hierarchical mesh structure:

• Top-level straps: Wide metal traces on upper layers providing low-resistance power delivery from pads to the core
• Power rings: Continuous metal loops around the chip periphery or block boundaries collecting power from pads
• Power stripes: Regularly spaced vertical and horizontal traces distributing power across the core area
• Standard cell rails: Fine-pitch power and ground traces in lower metal layers directly feeding standard cells
• Via stacks: Vertical connections linking power structures across metal layers

The mesh structure provides redundant current paths, reducing the impact of manufacturing defects and ensuring uniform voltage distribution.

IR Drop Analysis and Mitigation

IR drop occurs when current flowing through resistive power grid elements causes voltage reduction:

• Static IR drop: Voltage drop due to average DC current consumption, analyzed with average power estimates
• Dynamic IR drop: Transient voltage variations caused by switching activity, requiring vector-based simulation
• Worst-case analysis: Identifying maximum current scenarios that produce largest voltage drops
• Hot spot identification: Locating regions where IR drop exceeds acceptable limits

Mitigation strategies include adding power straps, widening existing traces, increasing via density, and redistributing high-power cells.

Electromigration Considerations

Electromigration is the gradual displacement of metal atoms due to electron flow, eventually causing open or short circuits:

• Current density limits: Each metal layer has maximum allowable current density based on wire width and temperature
• Average vs. peak current: Both average and RMS current contribute to electromigration stress
• Temperature dependence: Electromigration accelerates exponentially with temperature
• Wire sizing: Power grid elements must be sized to keep current density within safe limits
• Via redundancy: Multiple vias reduce current density through each individual via

Power grid design must account for electromigration to ensure reliability over the product lifetime, typically 10 or more years.

Multi-Voltage Domain Design

Modern SoCs employ multiple voltage domains to optimize power consumption:

• Voltage islands: Regions operating at different supply voltages, each requiring independent power distribution
• Level shifters: Interface cells converting signals between voltage domains, placed at domain boundaries
• Power switches: Transistors that can disconnect power to idle blocks, requiring careful placement and routing
• Isolation cells: Preventing undefined outputs from powered-down blocks from affecting active logic
• Always-on domains: Regions that maintain power during low-power states, requiring robust independent supply

Decoupling Capacitor Insertion

Decoupling capacitors provide local charge storage to maintain stable supply voltage during transient current demands:

• Placement strategy: Distributing decaps throughout the design, concentrated near high-switching-activity regions
• Capacitor types: Standard cell decaps, filler cells with capacitance, and dedicated capacitor structures
• Frequency response: Different capacitor sizes provide effective decoupling at different frequencies
• Area trade-offs: Balancing decap area against functional cell area and routing resources
• Automatic insertion: Tools can automatically place decaps in available whitespace after placement

Clock Tree Topologies

Several fundamental topologies serve different design requirements:

• H-tree: Symmetric branching structure providing inherently balanced delays to all endpoints
• Fishbone: Central spine with lateral branches, efficient for elongated floorplans
• Mesh: Grid of interconnected clock wires providing redundancy and low skew
• Hybrid: Combining topologies, often using mesh at top levels with tree structures locally
• Clock grid: Dense mesh driven by multiple distributed buffers, common in high-performance processors

The optimal topology depends on die size, clock frequency, skew requirements, and power constraints.

Skew and Latency Management

Clock skew represents the variation in clock arrival times at different sequential elements:

• Local skew: Difference in clock arrival between directly connected registers, critical for setup/hold timing
• Global skew: Maximum difference across all clock endpoints, affects worst-case timing analysis
• Useful skew: Intentionally introduced skew to help meet timing on critical paths
• On-chip variation (OCV): Manufacturing and environmental variations that affect skew unpredictably

CTS tools balance clock paths by inserting buffers, adjusting wire lengths, and using delay cells to achieve target skew values.

Buffer Insertion and Sizing

Clock buffers drive capacitive loads while maintaining signal integrity:

• Buffer tree construction: Building hierarchical buffer chains to drive clock loads
• Buffer sizing: Selecting appropriate drive strengths to balance delay, power, and slew rate
• Inverter pairs: Using pairs of inverters rather than buffers for better noise immunity
• Clock gating cells: Integrated clock enable (ICG) cells that combine gating logic with buffering
• Low-skew buffers: Specialized cells with matched rise/fall times for critical applications

Clock Gating Implementation

Clock gating reduces dynamic power by stopping clocks to inactive logic:

• RTL-level gating: Architectural clock enables identified during synthesis
• Sequential clock gating: Automatically inserting clock gates when register inputs are stable
• Hierarchical gating: Multi-level gating structure with coarse and fine-grain control
• Gating cell placement: Positioning clock gates to minimize impact on clock tree balance
• Enable timing: Ensuring gating signals arrive before clock edges to prevent glitches

Multi-Clock Domain Handling

Complex SoCs contain multiple clock domains requiring coordinated distribution:

• Independent trees: Separate clock trees for each domain with no shared buffering
• Derived clocks: Clocks generated by dividers or PLLs from a common source
• Clock domain crossing: Synchronizers at domain boundaries requiring controlled clock relationships
• Concurrent optimization: Balancing multiple clock trees simultaneously for consistent methodology
• Asynchronous interfaces: Handling communication between unrelated clock domains

Global Placement

Global placement establishes approximate cell locations across the entire chip:

• Analytical placement: Formulating placement as a mathematical optimization problem, minimizing a cost function representing wirelength
• Quadratic placement: Using quadratic wirelength models that enable efficient mathematical solutions
• Force-directed methods: Modeling nets as springs that pull connected cells together
• Partition-based methods: Recursively dividing the design and chip area into smaller subproblems
• Simulated annealing: Probabilistic optimization accepting temporarily worse solutions to escape local minima

Global placement produces an initial solution that detailed placement then refines.

Detailed Placement

Detailed placement legalizes and refines cell positions to fixed row locations:

• Legalization: Snapping cells to legal row positions and eliminating overlaps
• Cell spreading: Distributing cells evenly to avoid congestion hot spots
• Local optimization: Swapping adjacent cells to reduce local wirelength
• Cell mirroring: Flipping cells to align power rails and reduce routing conflicts
• Incremental improvement: Iteratively refining placement through local moves

Timing-Driven Placement

Timing-driven placement prioritizes meeting timing constraints:

• Net weighting: Assigning higher weights to timing-critical nets to pull connected cells closer
• Path-based optimization: Analyzing entire timing paths rather than individual nets
• Slack distribution: Allocating timing slack across path segments based on path criticality
• Concurrent timing analysis: Updating timing during placement iterations for accurate guidance
• Timing-driven legalization: Prioritizing timing over wirelength during detailed placement

Congestion-Aware Placement

Congestion-aware placement anticipates routing resource limitations:

• Congestion estimation: Predicting routing demand based on cell connectivity and locations
• Density control: Limiting local cell density to reserve routing resources
• Congestion-driven spreading: Dispersing cells away from high-congestion regions
• Pin density management: Avoiding excessive pin concentration in local areas
• Routing layer awareness: Considering available routing resources on different metal layers

Macro Placement

Macro placement handles large fixed-size blocks like memories and IP cores:

• Channel planning: Leaving routing channels between macros for signal paths
• Orientation optimization: Selecting macro orientations to minimize pin-to-logic distances
• Clustering: Grouping related macros (e.g., memory arrays) for efficient connectivity
• Halo regions: Defining keep-out areas around macros for routing or other constraints
• Abutment: Placing compatible macros edge-to-edge to share power rails or signals

Global Routing

Global routing assigns nets to routing regions without determining exact paths:

• Routing graph construction: Building a graph representing routing regions and their capacities
• Path assignment: Finding routes for each net through the routing graph
• Congestion management: Balancing routing demand across regions to avoid overflow
• Layer assignment: Determining which metal layers will carry each net segment
• Rip-up and reroute: Iteratively improving routes that cause congestion or timing violations

Global routing produces a routing plan that guides detailed routing while identifying potential congestion problems early.

Detailed Routing

Detailed routing creates actual metal and via geometries:

• Track assignment: Assigning wire segments to specific routing tracks
• Design rule compliance: Ensuring spacing, width, and via rules are satisfied
• Via optimization: Minimizing via count while maintaining connectivity
• Metal fill: Adding dummy metal to satisfy density requirements
• Antenna rule fixing: Adding diodes or adjusting routes to prevent gate oxide damage during manufacturing

Layer Assignment Strategies

Effective layer assignment improves routing efficiency and signal integrity:

• Preferred direction: Using horizontal routing on some layers, vertical on others to minimize vias
• Layer characteristics: Assigning fast signals to low-resistance upper metal layers
• Power routing: Reserving thick upper metals for power distribution
• Signal separation: Isolating sensitive analog signals from noisy digital nets
• Clock routing: Using dedicated layers or shielded routes for clock distribution

Via Optimization

Vias connect different metal layers but add resistance and manufacturing risk:

• Via minimization: Reducing via count through better layer assignment
• Multi-cut vias: Using multiple via cuts in parallel for lower resistance and better reliability
• Via enclosure: Ensuring adequate metal around vias per design rules
• Via stacking: Aligning vias vertically when connecting multiple layers
• Via-last optimization: Post-routing via insertion to improve timing or reliability

Special Net Routing

Certain nets require special routing treatment:

• Clock nets: Balanced routing with matched delays, often requiring manual guidance
• High-speed buses: Length-matched routing for timing-critical parallel signals
• Differential pairs: Closely-coupled traces maintaining controlled impedance and matching
• Power nets: Wide straps with low resistance, following power grid planning
• Shielded nets: Sensitive signals protected by grounded guard traces

Congestion Metrics

Quantifying congestion guides optimization efforts:

• Horizontal/vertical overflow: Number of routing tracks demanded beyond available capacity
• Global routing congestion: Congestion measured on the global routing graph
• Local density: Pin and cell concentration in small regions
• Layer utilization: Percentage of available tracks used on each metal layer
• Hot spot identification: Regions requiring focused optimization effort

Congestion Visualization

Visualization tools help engineers understand congestion patterns:

• Congestion maps: Color-coded displays showing congestion levels across the chip
• Layer-by-layer views: Examining congestion on individual routing layers
• Pin density plots: Identifying regions with excessive pin concentration
• Route path display: Visualizing actual routing to understand congestion causes
• Trend analysis: Tracking congestion changes across iterations

Congestion Relief Techniques

Multiple approaches address routing congestion:

• Cell spreading: Redistributing cells to reduce local density
• Blockage insertion: Adding placement blockages to force cells away from congested areas
• Channel widening: Increasing spacing between macros to provide more routing resources
• Pin swapping: Exchanging equivalent pins to reduce local congestion
• Gate cloning: Duplicating high-fanout drivers to reduce routing demand
• Layer promotion: Moving congested nets to less-utilized layers

Design-Level Congestion Solutions

Sometimes congestion requires design or methodology changes:

• Hierarchy restructuring: Reorganizing design hierarchy to improve connectivity
• Floor plan adjustment: Repositioning blocks to create better routing channels
• Logic restructuring: Modifying RTL to reduce high-fanout nets or bus widths
• Metal layer addition: Adding routing layers if technology permits
• Die size increase: Expanding available area when congestion is fundamental

Timing Analysis Integration

Timing analysis is embedded throughout the P&R flow:

• In-place timing: Continuous timing updates as placement and routing progress
• Incremental timing: Efficient updates that only recompute affected paths
• Path-based analysis: Considering complete timing paths rather than individual gates
• Multi-corner analysis: Simultaneous optimization across process, voltage, and temperature variations
• Statistical timing: Accounting for manufacturing variations probabilistically

Optimization Techniques

Tools apply various transformations to improve timing:

• Buffer insertion: Adding buffers to long nets to reduce delay
• Gate sizing: Increasing drive strength of cells on critical paths
• Threshold voltage swapping: Using faster (higher-leakage) cells where timing requires
• Wire sizing: Widening critical nets to reduce resistance
• Net topology optimization: Restructuring Steiner trees for better timing
• Useful skew: Adjusting clock arrival times to help meet timing

Hold Time Fixing

Hold violations occur when signals arrive too quickly at registers:

• Buffer insertion: Adding delay buffers to slow fast paths
• Delay cell insertion: Using specialized cells providing controlled delay
• Path detour: Lengthening wire paths to add delay
• Clock skew adjustment: Adjusting clock arrival to increase data path timing margin
• Post-CTS fixing: Most hold fixing occurs after clock tree synthesis when skew is known

Setup Time Optimization

Setup violations require reducing path delay:

• Path restructuring: Placing cells closer together on critical paths
• Cell upsizing: Using larger cells with higher drive strength
• Logic restructuring: Modifying logic structure to reduce critical path depth
• Net optimization: Minimizing RC delay on critical interconnects
• Layer promotion: Moving critical nets to faster metal layers

Multi-Mode Multi-Corner Optimization

Designs must meet timing across all operating conditions:

• Process corners: Fast, typical, and slow transistor characteristics
• Voltage corners: Nominal and reduced supply voltages
• Temperature corners: Operating temperature range extremes
• Functional modes: Different clock frequencies or operational states
• Concurrent optimization: Optimizing across all scenarios simultaneously

Closure Methodology

Systematic approaches improve closure efficiency:

• Incremental flows: Building upon previous results rather than starting from scratch
• Convergent optimization: Ensuring each iteration makes progress toward closure
• Priority-based fixing: Addressing worst violations first
• Margin management: Trading timing margin for other objectives as closure progresses
• Checkpoint strategy: Saving intermediate results to enable recovery from failed experiments

Post-Route Optimization

Fine-tuning after routing completes:

• In-place optimization: Improving cells without changing locations significantly
• Wire optimization: Adjusting routes for better timing or integrity
• Via optimization: Adding redundant vias or optimizing via positions
• Final buffer insertion: Adding buffers where needed after final timing analysis
• Leakage optimization: Swapping to lower-leakage cells on non-critical paths

Signoff Timing Closure

Meeting timing requirements under signoff analysis conditions:

• Signoff-quality extraction: Using accurate parasitic extraction for final timing
• Advanced OCV: Applying on-chip variation derates for realistic worst-case analysis
• AOCV/POCV: Path-based or parametric OCV for more accurate variation modeling
• IR drop derating: Accounting for voltage drop impact on cell delays
• Noise-aware timing: Including crosstalk effects in timing analysis

Physical Verification Closure

Ensuring the design meets all manufacturing requirements:

• Design rule checking (DRC): Verifying all geometry rules are satisfied
• Layout vs. schematic (LVS): Confirming physical layout matches schematic intent
• Antenna checking: Ensuring manufacturing processes cannot damage gate oxides
• Density checking: Verifying metal density meets manufacturing requirements
• Electrical rule checking (ERC): Validating power connections and electrical constraints

Types of ECOs

Different ECO types require different implementation approaches:

• Functional ECOs: Logic changes to fix bugs or add functionality
• Timing ECOs: Modifications to fix timing violations
• Power ECOs: Changes to reduce power consumption
• Metal-only ECOs: Changes that only modify routing layers, preserving existing silicon
• Engineering samples ECOs: Minor fixes for prototype debugging

ECO Methodology

Systematic ECO implementation minimizes risk and effort:

• Change isolation: Limiting ECO impact to minimize ripple effects
• Spare cell utilization: Using pre-placed spare gates for functional changes
• Incremental placement: Placing new cells with minimal disturbance to existing layout
• Incremental routing: Routing ECO nets while preserving existing routes
• Targeted verification: Focusing verification on changed areas

Spare Cell Strategies

Spare cells facilitate post-silicon modifications:

• Spare cell types: Variety of gates (NAND, NOR, inverters, flip-flops) distributed throughout design
• Distribution strategy: Placing spare cells uniformly or concentrated near likely change areas
• Spare cell routing: Pre-connecting power and ground, leaving signal pins available
• Utilization tracking: Monitoring spare cell usage across ECO iterations
• Spare macros: Including spare memory bits or I/O cells for larger changes

Metal-Only ECOs

Metal-only ECOs modify routing without changing transistor layers:

• Cost advantages: Only routing masks need replacement, significantly reducing NRE costs
• Time savings: Shorter manufacturing cycle for metal-only respins
• Limitations: Cannot add new transistors; must use existing spare cells
• Layer restrictions: Sometimes only upper metal layers can be modified
• Verification requirements: Must verify metal-only changes do not impact other design aspects

ECO Verification

Thorough verification ensures ECO correctness:

• Formal equivalence: Proving modified netlist matches updated RTL
• Incremental timing: Analyzing timing impact of changes
• Physical verification: Running DRC/LVS on modified regions
• Regression testing: Ensuring existing functionality is preserved
• Change documentation: Recording all modifications for future reference

Machine Learning in P&R

Machine learning is increasingly applied to physical design:

• Congestion prediction: ML models predicting routing congestion before detailed routing
• Timing prediction: Estimating post-route timing during placement
• Parameter tuning: Automatically optimizing tool settings for design characteristics
• Quality assessment: Predicting final design quality from intermediate metrics
• Design space exploration: Efficiently searching large parameter spaces

3D IC Implementation

Three-dimensional integration introduces new P&R challenges:

• Through-silicon via (TSV) planning: Placing vertical connections between die
• Multi-die floor planning: Coordinating placement across stacked die
• Thermal-aware placement: Managing heat dissipation in 3D structures
• Inter-die routing: Optimizing signal paths across die boundaries
• Power delivery: Distributing power through multiple die levels

Advanced Node Challenges

Leading-edge process nodes present unique P&R challenges:

• Multiple patterning: Decomposing layouts for multi-pass lithography
• Complex design rules: Managing hundreds of nuanced design rules
• Track patterns: Routing on fixed track grids with restricted via positions
• Cell architecture: Accommodating new transistor structures (FinFET, GAA)
• Manufacturability: Ensuring designs yield well in manufacturing